Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	129630	1			T73	126		T74	4		T78	16
values[2]	8234	1			T74	2		T262	1		T549	2
values[3]	2970	1			T550	1		T554	1		T836	1
values[4]	1832	1			T836	1		T555	1		T551	14
values[5]	1187	1			T836	1		T555	1		T551	5
values[6]	758	1			T836	1		T555	1		T551	6
values[7]	542	1			T836	1		T555	1		T551	10
values[8]	429	1			T836	1		T555	1		T551	3
values[9]	436	1			T836	1		T555	1		T551	11
values[10]	383	1			T836	1		T555	1		T551	3
values[11]	308	1			T836	1		T555	1		T551	6
values[12]	302	1			T836	1		T555	1		T551	11
values[13]	297	1			T836	1		T555	1		T551	3
values[14]	280	1			T836	1		T555	1		T551	3
values[15]	232	1			T836	1		T555	1		T551	3
values[16]	262	1			T836	1		T555	1		T551	15
values[17]	227	1			T836	1		T555	1		T551	15
values[18]	204	1			T836	1		T555	1		T551	7
values[19]	234	1			T836	1		T555	1		T551	3
values[20]	182	1			T836	1		T555	1		T551	7
values[21]	187	1			T836	1		T555	1		T551	9
values[22]	195	1			T836	1		T555	1		T551	13
values[23]	174	1			T836	1		T555	1		T551	6
values[24]	205	1			T836	1		T555	1		T551	11
values[25]	216	1			T836	1		T555	1		T551	4
values[26]	207	1			T836	1		T555	1		T551	8
values[27]	230	1			T836	1		T555	1		T551	5
values[28]	210	1			T836	1		T555	1		T551	7
values[29]	193	1			T836	1		T555	1		T551	4
values[30]	229	1			T836	1		T555	1		T551	16
values[31]	178	1			T836	1		T555	1		T551	10
values[32]	176	1			T836	1		T555	1		T551	7
values[33]	176	1			T836	1		T555	1		T551	8
values[34]	206	1			T836	1		T555	1		T551	4
values[35]	210	1			T836	1		T555	1		T551	3
values[36]	185	1			T836	1		T555	1		T551	6
values[37]	200	1			T836	1		T555	1		T551	4
values[38]	222	1			T836	1		T555	2		T551	4
values[39]	224	1			T836	1		T555	1		T551	5
values[40]	180	1			T836	1		T555	1		T551	5
values[41]	208	1			T836	1		T555	1		T551	8
values[42]	176	1			T836	1		T555	1		T551	3
values[43]	176	1			T836	1		T555	1		T551	13
values[44]	201	1			T836	1		T555	1		T551	5
values[45]	213	1			T836	1		T555	1		T551	9
values[46]	185	1			T836	1		T555	1		T551	5
values[47]	181	1			T836	1		T555	1		T551	5
values[48]	181	1			T836	1		T555	1		T551	3
values[49]	188	1			T836	1		T555	1		T551	9
values[50]	213	1			T836	1		T555	1		T551	9
values[51]	166	1			T836	1		T555	1		T551	4
values[52]	174	1			T836	1		T555	1		T551	10
values[53]	192	1			T836	1		T555	1		T551	7
values[54]	182	1			T836	1		T555	1		T551	15
values[55]	167	1			T836	2		T555	1		T551	15
values[56]	188	1			T836	1		T555	1		T551	8
values[57]	202	1			T836	1		T555	1		T551	4
values[58]	197	1			T836	1		T555	1		T551	11
values[59]	159	1			T836	1		T555	1		T551	15
values[60]	155	1			T836	1		T555	1		T551	5
values[61]	147	1			T836	1		T555	1		T551	4
values[62]	138	1			T836	1		T555	1		T551	8
values[63]	117	1			T836	1		T555	1		T930	2
values[64]	94	1			T836	1		T555	1		T930	2
values[65]	98	1			T836	1		T555	1		T930	2
values[66]	97	1			T836	1		T555	1		T930	2
values[67]	134	1			T836	1		T555	1		T930	2
values[68]	88	1			T836	1		T555	1		T930	2
values[69]	75	1			T836	1		T555	1		T930	2
values[70]	54	1			T836	1		T555	1		T930	2
values[71]	76	1			T836	1		T555	1		T930	2
values[72]	86	1			T836	1		T555	1		T930	2
values[73]	62	1			T836	1		T555	1		T930	2
values[74]	59	1			T836	1		T555	1		T930	2
values[75]	45	1			T836	1		T555	1		T930	2
values[76]	42	1			T836	1		T555	1		T930	2
values[77]	39	1			T836	1		T555	1		T930	2
values[78]	52	1			T836	1		T555	1		T930	2
values[79]	51	1			T836	1		T555	1		T930	2
values[80]	42	1			T836	1		T555	1		T930	2
values[81]	44	1			T836	1		T555	1		T930	2
values[82]	32	1			T836	1		T555	1		T930	2
values[83]	32	1			T836	1		T555	1		T930	2
values[84]	38	1			T836	1		T555	1		T930	2
values[85]	40	1			T836	1		T555	1		T930	2
values[86]	42	1			T836	1		T555	1		T930	2
values[87]	47	1			T836	1		T555	1		T930	2
values[88]	51	1			T836	1		T555	1		T930	2
values[89]	48	1			T836	1		T555	1		T930	2
values[90]	48	1			T836	1		T555	4		T930	2
values[91]	46	1			T836	1		T555	8		T930	2
values[92]	41	1			T836	1		T555	2		T930	2
values[93]	49	1			T836	1		T555	3		T930	2
values[94]	36	1			T836	1		T555	1		T930	2
values[95]	41	1			T836	1		T555	2		T930	2
values[96]	37	1			T836	1		T555	6		T930	3
values[97]	45	1			T836	1		T555	3		T930	5
values[98]	55	1			T836	1		T555	3		T930	2
values[99]	42	1			T836	1		T555	1		T930	3
values[100]	44	1			T836	1		T555	1		T930	2
values[101]	43	1			T836	1		T555	1		T930	2
values[102]	52	1			T836	1		T555	2		T930	4
values[103]	60	1			T836	1		T555	3		T930	5
values[104]	46	1			T836	1		T555	2		T930	3
values[105]	50	1			T836	1		T555	3		T930	3
values[106]	55	1			T836	1		T555	1		T930	6
values[107]	51	1			T836	1		T555	2		T930	4
values[108]	67	1			T836	1		T555	8		T930	6
values[109]	50	1			T836	1		T555	5		T930	3
values[110]	45	1			T836	1		T555	1		T930	4
values[111]	56	1			T836	1		T555	1		T930	3
values[112]	39	1			T836	1		T555	3		T930	4
values[113]	38	1			T836	1		T555	1		T930	3
values[114]	50	1			T836	3		T555	1		T930	9
values[115]	52	1			T836	2		T555	1		T930	2
values[116]	48	1			T836	2		T555	1		T930	5
values[117]	60	1			T836	5		T555	1		T930	8
values[118]	68	1			T836	4		T555	2		T930	7
values[119]	54	1			T836	1		T555	1		T930	5
values[120]	68	1			T836	1		T555	2		T930	2
values[121]	53	1			T836	1		T555	1		T930	4
values[122]	61	1			T836	1		T555	1		T930	10
values[123]	53	1			T836	1		T555	7		T930	3
values[124]	54	1			T836	1		T555	1		T930	5
values[125]	58	1			T836	1		T555	2		T930	5
values[126]	130	1			T836	3		T555	5		T930	7
values[127]	795	1			T836	37		T555	24		T930	70
values[128]	7237	1			T836	396		T555	258		T930	703