Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	425	1			T73	4		T548	2		T551	1
all_values[1]	462	1			T73	4		T836	1		T551	1
all_values[2]	481	1			T73	2		T562	1		T446	3
all_values[3]	442	1			T73	2		T836	1		T553	1
all_values[4]	436	1			T73	7		T548	1		T446	1
all_values[5]	458	1			T73	1		T125	1		T548	1
all_values[6]	475	1			T73	6		T548	1		T836	1
all_values[7]	452	1			T73	2		T125	1		T551	1
all_values[8]	455	1			T73	2		T836	1		T553	1
all_values[9]	452	1			T73	1		T836	1		T446	3
all_values[10]	429	1			T73	1		T446	1		T634	1
all_values[11]	431	1			T73	1		T836	1		T555	1
all_values[12]	419	1			T73	2		T555	1		T446	5
all_values[13]	460	1			T73	1		T555	2		T446	3
all_values[14]	466	1			T73	4		T125	1		T553	1
all_values[15]	458	1			T73	1		T446	2		T634	3
all_values[16]	464	1			T73	1		T555	1		T446	2
all_values[17]	431	1			T125	1		T446	3		T432	1
all_values[18]	449	1			T73	2		T836	1		T553	1
all_values[19]	445	1			T73	4		T446	1		T496	1
all_values[20]	453	1			T73	2		T553	1		T446	2
all_values[21]	451	1			T73	7		T125	1		T446	2
all_values[22]	475	1			T73	5		T555	1		T446	4
all_values[23]	439	1			T73	5		T836	1		T446	3
all_values[24]	454	1			T73	3		T125	1		T555	1
all_values[25]	449	1			T73	5		T836	1		T555	1
all_values[26]	461	1			T73	3		T836	1		T446	3
all_values[27]	395	1			T73	1		T125	1		T262	1
all_values[28]	442	1			T73	4		T836	1		T551	3
all_values[29]	434	1			T73	2		T836	1		T555	1
all_values[30]	435	1			T73	3		T446	2		T432	1
all_values[31]	406	1			T73	1		T446	6		T634	6
all_values[32]	462	1			T836	1		T555	1		T446	6
all_values[33]	433	1			T73	3		T548	1		T551	1
all_values[34]	441	1			T73	1		T446	3		T432	1
all_values[35]	467	1			T73	2		T125	1		T836	1
all_values[36]	441	1			T73	1		T555	1		T446	3
all_values[37]	461	1			T73	8		T446	2		T432	1
all_values[38]	429	1			T73	1		T446	4		T634	2
all_values[39]	482	1			T73	4		T555	1		T551	1
all_values[40]	476	1			T73	2		T446	3		T634	2
all_values[41]	469	1			T73	1		T553	1		T555	1
all_values[42]	479	1			T73	2		T551	1		T446	4
all_values[43]	436	1			T73	5		T446	3		T496	1
all_values[44]	420	1			T73	2		T836	1		T446	4
all_values[45]	439	1			T73	3		T125	1		T553	1
all_values[46]	446	1			T73	2		T555	1		T446	5
all_values[47]	452	1			T73	3		T836	1		T446	3
all_values[48]	441	1			T73	2		T446	2		T634	3
all_values[49]	441	1			T73	3		T548	2		T836	1