Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3446	1			T73	16		T125	2		T705	1
all_values[1]	3461	1			T73	30		T125	3		T446	17
all_values[2]	3557	1			T73	27		T125	3		T446	20
all_values[3]	3451	1			T73	21		T125	3		T262	2
all_values[4]	3559	1			T73	28		T125	3		T262	1
all_values[5]	3425	1			T73	30		T125	1		T446	25
all_values[6]	3433	1			T73	26		T125	1		T446	19
all_values[7]	3399	1			T73	24		T125	1		T262	1
all_values[8]	3422	1			T73	29		T125	4		T705	1
all_values[9]	3446	1			T73	33		T125	1		T705	1
all_values[10]	3494	1			T73	28		T125	2		T446	22
all_values[11]	3422	1			T73	24		T262	1		T446	18
all_values[12]	3432	1			T73	25		T125	2		T446	32
all_values[13]	3415	1			T73	33		T125	2		T705	1
all_values[14]	3511	1			T73	39		T125	3		T446	28
all_values[15]	3397	1			T73	29		T125	3		T262	1
all_values[16]	3603	1			T73	38		T125	2		T262	1
all_values[17]	3403	1			T73	28		T125	3		T446	20
all_values[18]	3374	1			T73	23		T125	1		T705	1
all_values[19]	3488	1			T73	38		T125	4		T446	25
all_values[20]	3358	1			T73	19		T125	2		T446	29
all_values[21]	3549	1			T73	41		T125	2		T446	17
all_values[22]	3447	1			T73	32		T446	19		T634	15
all_values[23]	3497	1			T73	36		T125	2		T446	27
all_values[24]	3382	1			T73	24		T125	2		T446	26
all_values[25]	3444	1			T73	23		T262	1		T705	2
all_values[26]	3552	1			T73	32		T125	1		T446	22
all_values[27]	3543	1			T73	32		T125	1		T262	2
all_values[28]	3496	1			T73	31		T125	2		T446	20
all_values[29]	3529	1			T73	36		T125	2		T446	21
all_values[30]	3388	1			T73	24		T125	3		T446	22
all_values[31]	3460	1			T73	23		T125	4		T446	21
all_values[32]	3467	1			T73	37		T125	2		T446	18
all_values[33]	3435	1			T73	26		T125	4		T446	23
all_values[34]	3465	1			T73	29		T125	5		T446	23
all_values[35]	3353	1			T73	27		T125	3		T705	2
all_values[36]	3356	1			T73	29		T125	2		T705	1
all_values[37]	3393	1			T73	26		T125	2		T705	2
all_values[38]	3472	1			T73	29		T125	2		T705	1
all_values[39]	3321	1			T73	26		T125	3		T262	2
all_values[40]	3349	1			T73	27		T125	2		T705	1
all_values[41]	3459	1			T73	43		T125	3		T446	21
all_values[42]	3412	1			T73	41		T125	2		T446	26
all_values[43]	3508	1			T73	25		T262	1		T705	1
all_values[44]	3369	1			T73	29		T125	3		T446	27
all_values[45]	3485	1			T73	25		T125	2		T262	1
all_values[46]	3489	1			T73	22		T125	2		T446	25
all_values[47]	3484	1			T73	28		T125	2		T705	1
all_values[48]	3472	1			T73	34		T125	1		T446	20
all_values[49]	3442	1			T73	24		T125	1		T262	1
all_values[50]	3382	1			T73	30		T125	3		T446	30
all_values[51]	3536	1			T73	34		T125	1		T262	1
all_values[52]	3488	1			T73	44		T125	2		T446	27
all_values[53]	3418	1			T73	24		T125	3		T446	22
all_values[54]	3451	1			T73	36		T125	2		T705	1
all_values[55]	3332	1			T73	30		T125	2		T262	1
all_values[56]	3372	1			T73	32		T446	22		T634	17
all_values[57]	3468	1			T73	36		T446	22		T432	2
all_values[58]	3450	1			T73	45		T125	3		T446	17
all_values[59]	3486	1			T73	37		T125	2		T262	1
all_values[60]	3355	1			T73	22		T125	4		T705	1
all_values[61]	3469	1			T73	31		T125	1		T446	25
all_values[62]	3411	1			T73	25		T125	1		T262	1
all_values[63]	3403	1			T73	32		T125	3		T446	32