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LINE 32929
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32930
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32931
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32932
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32933
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32934
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32935
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32936
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32937
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32938
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32939
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32940
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32941
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32942
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32943
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32944
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32945
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32946
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32947
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32948
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32949
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32950
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T288,T36,T37 |
LINE 32951
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32952
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32953
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32954
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32955
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32956
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32957
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32958
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32959
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32960
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32961
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32962
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32963
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32964
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32965
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32966
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32967
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32968
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32969
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32970
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32971
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T12,T36,T37 |
LINE 32972
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32973
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32974
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32975
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32976
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32977
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32978
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32979
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32980
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32981
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32982
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32983
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32984
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32985
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32986
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32987
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32988
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32989
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32990
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32991
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32992
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32993
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32994
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32995
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32996
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32997
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32998
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 32999
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33000
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33001
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33002
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33003
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33004
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33005
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33006
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33007
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33008
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33009
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33010
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T36,T37,T38 |
LINE 33011
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T30,T58 |
LINE 33012
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33013
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33014
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33015
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33016
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33017
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33018
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33019
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33020
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33021
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33022
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33023
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33024
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33025
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33026
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33027
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33028
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33029
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33030
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33031
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33032
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33033
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33034
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33035
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33036
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33037
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33038
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33039
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33040
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33041
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33042
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33043
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33044
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T33 |
LINE 33045
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T31,T19,T1 |
LINE 33046
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T31,T19 |
LINE 33047
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T19,T86 |
LINE 33048
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33049
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T19,T86 |
LINE 33050
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T19,T86 |
LINE 33051
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T19,T86 |
LINE 33052
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33053
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33054
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33055
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33056
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33057
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33058
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33059
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33060
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T113,T114 |
LINE 33061
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33062
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33063
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33064
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33065
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33066
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33067
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33068
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_0_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33069
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_1_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33070
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_2_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33071
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33072
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33073
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33074
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33075
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33076
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_0_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33077
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_1_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33078
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_2_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33079
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_3_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33080
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_4_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33081
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_5_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33082
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_6_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33083
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_7_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33084
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33085
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33086
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33087
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33088
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33089
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33090
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33091
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33092
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33093
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33094
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33095
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33096
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33097
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33098
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33099
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33100
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_CAUSE_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33103
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 33103
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T6,T30,T58 |
LINE 33107
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1 & (~reg_be))))) | (addr_hit[79] & ((|(4'b1 & (~reg_be))))) | (addr_hit[80] & ((|(4'b1 & (~reg_be))))) | (addr_hit[81] & ((|(4'b1 & (~reg_be))))) | (addr_hit[82] & ((|(4'b1 & (~reg_be))))) | (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | (addr_hit[84] & ((|(4'b1 & (~reg_be))))) | (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | (addr_hit[87] & ((|(4'b1 & (~reg_be))))) | (addr_hit[88] & ((|(4'b1 & (~reg_be))))) | (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | (addr_hit[94] & ((|(4'b1 & (~reg_be))))) | (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | (addr_hit[96] & ((|(4'b1 & (~reg_be))))) | (addr_hit[97] & ((|(4'b1 & (~reg_be))))) | (addr_hit[98] & ((|(4'b1 & (~reg_be))))) | (addr_hit[99] & ((|(4'b1 & (~reg_be))))) | (addr_hit[100] & ((|(4'b1 & (~reg_be))))) | (addr_hit[101] & ((|(4'b1 & (~reg_be))))) | (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | (addr_hit[104] & ((|(4'b1 & (~reg_be))))) | (addr_hit[105] & ((|(4'b1 & (~reg_be))))) | (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | (addr_hit[107] & ((|(4'b1 & (~reg_be))))) | (addr_hit[108] & ((|(4'b1 & (~reg_be))))) | (addr_hit[109] & ((|(4'b1 & (~reg_be))))) | (addr_hit[110] & ((|(4'b1 & (~reg_be))))) | (addr_hit[111] & ((|(4'b1 & (~reg_be))))) | (addr_hit[112] & ((|(4'b1 & (~reg_be))))) | (addr_hit[113] & ((|(4'b1 & (~reg_be))))) | (addr_hit[114] & ((|(4'b1 & (~reg_be))))) | (addr_hit[115] & ((|(4'b1 & (~reg_be))))) | (addr_hit[116] & ((|(4'b1 & (~reg_be))))) | (addr_hit[117] & ((|(4'b1 & (~reg_be))))) | (addr_hit[118] & ((|(4'b1 & (~reg_be))))) | (addr_hit[119] & ((|(4'b1 & (~reg_be))))) | (addr_hit[120] & ((|(4'b1 & (~reg_be))))) | (addr_hit[121] & ((|(4'b1 & (~reg_be))))) | (addr_hit[122] & ((|(4'b1 & (~reg_be))))) | (addr_hit[123] & ((|(4'b1 & (~reg_be))))) | (addr_hit[124] & ((|(4'b1 & (~reg_be))))) | (addr_hit[125] & ((|(4'b1 & (~reg_be))))) | (addr_hit[126] & ((|(4'b1 & (~reg_be))))) | (addr_hit[127] & ((|(4'b1 & (~reg_be))))) | (addr_hit[128] & ((|(4'b1 & (~reg_be))))) | (addr_hit[129] & ((|(4'b1 & (~reg_be))))) | (addr_hit[130] & ((|(4'b1 & (~reg_be))))) | (addr_hit[131] & ((|(4'b1 & (~reg_be))))) | (addr_hit[132] & ((|(4'b1 & (~reg_be))))) | (addr_hit[133] & ((|(4'b1 & (~reg_be))))) | (addr_hit[134] & ((|(4'b1 & (~reg_be))))) | (addr_hit[135] & ((|(4'b1 & (~reg_be))))) | (addr_hit[136] & ((|(4'b1 & (~reg_be))))) | (addr_hit[137] & ((|(4'b1 & (~reg_be))))) | (addr_hit[138] & ((|(4'b1 & (~reg_be))))) | (addr_hit[139] & ((|(4'b1 & (~reg_be))))) | (addr_hit[140] & ((|(4'b1 & (~reg_be))))) | (addr_hit[141] & ((|(4'b1 & (~reg_be))))) | (addr_hit[142] & ((|(4'b1 & (~reg_be))))) | (addr_hit[143] & ((|(4'b1 & (~reg_be))))) | (addr_hit[144] & ((|(4'b1 & (~reg_be))))) | (addr_hit[145] & ((|(4'b1 & (~reg_be))))) | (addr_hit[146] & ((|(4'b1 & (~reg_be))))) | (addr_hit[147] & ((|(4'b1 & (~reg_be))))) | (addr_hit[148] & ((|(4'b1 & (~reg_be))))) | (addr_hit[149] & ((|(4'b1 & (~reg_be))))) | (addr_hit[150] & ((|(4'b1 & (~reg_be))))) | (addr_hit[151] & ((|(4'b1 & (~reg_be))))) | (addr_hit[152] & ((|(4'b1 & (~reg_be))))) | (addr_hit[153] & ((|(4'b1 & (~reg_be))))) | (addr_hit[154] & ((|(4'b1 & (~reg_be))))) | (addr_hit[155] & ((|(4'b1 & (~reg_be))))) | (addr_hit[156] & ((|(4'b1 & (~reg_be))))) | (addr_hit[157] & ((|(4'b1 & (~reg_be))))) | (addr_hit[158] & ((|(4'b1 & (~reg_be))))) | (addr_hit[159] & ((|(4'b1 & (~reg_be))))) | (addr_hit[160] & ((|(4'b1 & (~reg_be))))) | (addr_hit[161] & ((|(4'b1 & (~reg_be))))) | (addr_hit[162] & ((|(4'b1 & (~reg_be))))) | (addr_hit[163] & ((|(4'b1 & (~reg_be))))) | (addr_hit[164] & ((|(4'b1 & (~reg_be))))) | (addr_hit[165] & ((|(4'b1 & (~reg_be))))) | (addr_hit[166] & ((|(4'b1 & (~reg_be))))) | (addr_hit[167] & ((|(4'b1 & (~reg_be))))) | (addr_hit[168] & ((|(4'b1 & (~reg_be))))) | (addr_hit[169] & ((|(4'b1 & (~reg_be))))) | (addr_hit[170] & ((|(4'b1 & (~reg_be))))) | (addr_hit[171] & ((|(4'b1 & (~reg_be))))) | (addr_hit[172] & ((|(4'b1 & (~reg_be))))) | (addr_hit[173] & ((|(4'b1 & (~reg_be))))) | (addr_hit[174] & ((|(4'b1 & (~reg_be))))) | (addr_hit[175] & ((|(4'b1 & (~reg_be))))) | (addr_hit[176] & ((|(4'b1 & (~reg_be))))) | (addr_hit[177] & ((|(4'b1 & (~reg_be))))) | (addr_hit[178] & ((|(4'b1 & (~reg_be))))) | (addr_hit[179] & ((|(4'b1 & (~reg_be))))) | (addr_hit[180] & ((|(4'b1 & (~reg_be))))) | (addr_hit[181] & ((|(4'b1 & (~reg_be))))) | (addr_hit[182] & ((|(4'b1 & (~reg_be))))) | (addr_hit[183] & ((|(4'b1 & (~reg_be))))) | (addr_hit[184] & ((|(4'b1 & (~reg_be))))) | (addr_hit[185] & ((|(4'b1 & (~reg_be))))) | (addr_hit[186] & ((|(4'b1 & (~reg_be))))) | (addr_hit[187] & ((|(4'b1 & (~reg_be))))) | (addr_hit[188] & ((|(4'b1 & (~reg_be))))) | (addr_hit[189] & ((|(4'b1 & (~reg_be))))) | (addr_hit[190] & ((|(4'b1 & (~reg_be))))) | (addr_hit[191] & ((|(4'b1 & (~reg_be))))) | (addr_hit[192] & ((|(4'b1 & (~reg_be))))) | (addr_hit[193] & ((|(4'b1 & (~reg_be))))) | (addr_hit[194] & ((|(4'b1 & (~reg_be))))) | (addr_hit[195] & ((|(4'b1 & (~reg_be))))) | (addr_hit[196] & ((|(4'b1 & (~reg_be))))) | (addr_hit[197] & ((|(4'b1 & (~reg_be))))) | (addr_hit[198] & ((|(4'b1 & (~reg_be))))) | (addr_hit[199] & ((|(4'b1 & (~reg_be))))) | (addr_hit[200] & ((|(4'b1 & (~reg_be))))) | (addr_hit[201] & ((|(4'b1 & (~reg_be))))) | (addr_hit[202] & ((|(4'b1 & (~reg_be))))) | (addr_hit[203] & ((|(4'b1 & (~reg_be))))) | (addr_hit[204] & ((|(4'b1 & (~reg_be))))) | (addr_hit[205] & ((|(4'b1 & (~reg_be))))) | (addr_hit[206] & ((|(4'b1 & (~reg_be))))) | (addr_hit[207] & ((|(4'b1 & (~reg_be))))) | (addr_hit[208] & ((|(4'b1 & (~reg_be))))) | (addr_hit[209] & ((|(4'b1 & (~reg_be))))) | (addr_hit[210] & ((|(4'b1 & (~reg_be))))) | (addr_hit[211] & ((|(4'b1 & (~reg_be))))) | (addr_hit[212] & ((|(4'b1 & (~reg_be))))) | (addr_hit[213] & ((|(4'b1 & (~reg_be))))) | (addr_hit[214] & ((|(4'b1 & (~reg_be))))) | (addr_hit[215] & ((|(4'b1 & (~reg_be))))) | (addr_hit[216] & ((|(4'b1 & (~reg_be))))) | (addr_hit[217] & ((|(4'b1 & (~reg_be))))) | (addr_hit[218] & ((|(4'b1 & (~reg_be))))) | (addr_hit[219] & ((|(4'b1 & (~reg_be))))) | (addr_hit[220] & ((|(4'b1 & (~reg_be))))) | (addr_hit[221] & ((|(4'b1 & (~reg_be))))) | (addr_hit[222] & ((|(4'b1 & (~reg_be))))) | (addr_hit[223] & ((|(4'b1 & (~reg_be))))) | (addr_hit[224] & ((|(4'b1 & (~reg_be))))) | (addr_hit[225] & ((|(4'b1 & (~reg_be))))) | (addr_hit[226] & ((|(4'b1 & (~reg_be))))) | (addr_hit[227] & ((|(4'b1 & (~reg_be))))) | (addr_hit[228] & ((|(4'b1 & (~reg_be))))) | (addr_hit[229] & ((|(4'b1 & (~reg_be))))) | (addr_hit[230] & ((|(4'b1 & (~reg_be))))) | (addr_hit[231] & ((|(4'b1 & (~reg_be))))) | (addr_hit[232] & ((|(4'b1 & (~reg_be))))) | (addr_hit[233] & ((|(4'b1 & (~reg_be))))) | (addr_hit[234] & ((|(4'b1 & (~reg_be))))) | (addr_hit[235] & ((|(4'b1 & (~reg_be))))) | (addr_hit[236] & ((|(4'b1 & (~reg_be))))) | (addr_hit[237] & ((|(4'b1 & (~reg_be))))) | (addr_hit[238] & ((|(4'b1 & (~reg_be))))) | (addr_hit[239] & ((|(4'b1 & (~reg_be))))) | (addr_hit[240] & ((|(4'b1 & (~reg_be))))) | (addr_hit[241] & ((|(4'b1 & (~reg_be))))) | (addr_hit[242] & ((|(4'b1 & (~reg_be))))) | (addr_hit[243] & ((|(4'b1 & (~reg_be))))) | (addr_hit[244] & ((|(4'b1 & (~reg_be))))) | (addr_hit[245] & ((|(4'b1 & (~reg_be))))) | (addr_hit[246] & ((|(4'b1 & (~reg_be))))) | (addr_hit[247] & ((|(4'b1 & (~reg_be))))) | (addr_hit[248] & ((|(4'b1 & (~reg_be))))) | (addr_hit[249] & ((|(4'b1 & (~reg_be))))) | (addr_hit[250] & ((|(4'b1 & (~reg_be))))) | (addr_hit[251] & ((|(4'b1 & (~reg_be))))) | (addr_hit[252] & ((|(4'b1 & (~reg_be))))) | (addr_hit[253] & ((|(4'b1 & (~reg_be))))) | (addr_hit[254] & ((|(4'b1 & (~reg_be))))) | (addr_hit[255] & ((|(4'b1 & (~reg_be))))) | (addr_hit[256] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[257] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[258] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[259] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[260] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[261] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[262] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[263] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[264] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[265] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[266] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[267] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[268] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[269] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[270] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[271] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[272] & ((|(4'b0111 & (~reg_be))))) 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(addr_hit[294] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[295] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[296] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[297] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[298] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[299] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[300] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[301] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[302] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[303] & ((|(4'b1 & (~reg_be))))) | (addr_hit[304] & ((|(4'b1 & (~reg_be))))) | (addr_hit[305] & ((|(4'b1 & (~reg_be))))) | (addr_hit[306] & ((|(4'b1 & (~reg_be))))) | (addr_hit[307] & ((|(4'b1 & (~reg_be))))) | (addr_hit[308] & ((|(4'b1 & (~reg_be))))) | (addr_hit[309] & ((|(4'b1 & (~reg_be))))) | (addr_hit[310] & ((|(4'b1 & (~reg_be))))) | (addr_hit[311] & ((|(4'b1 & (~reg_be))))) | (addr_hit[312] & ((|(4'b1 & (~reg_be))))) | (addr_hit[313] & ((|(4'b1 & (~reg_be))))) | (addr_hit[314] & ((|(4'b1 & (~reg_be))))) | (addr_hit[315] & ((|(4'b1 & (~reg_be))))) | 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| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Not Covered | |