Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156987	1			T75	15		T76	50		T77	63
values[2]	14903	1			T77	3		T271	1		T469	5
values[3]	7573	1			T271	1		T532	1		T472	1
values[4]	3412	1			T271	1		T689	95		T866	1
values[5]	1247	1			T271	1		T689	25		T866	1
values[6]	573	1			T271	1		T866	1		T871	1
values[7]	383	1			T271	1		T866	1		T871	1
values[8]	235	1			T271	1		T866	1		T871	1
values[9]	193	1			T271	1		T866	1		T871	1
values[10]	176	1			T271	1		T866	1		T871	1
values[11]	158	1			T271	1		T866	1		T871	1
values[12]	172	1			T271	1		T866	1		T871	1
values[13]	118	1			T271	1		T866	1		T871	1
values[14]	112	1			T271	1		T866	1		T871	1
values[15]	89	1			T271	1		T866	1		T871	1
values[16]	94	1			T271	1		T866	1		T871	1
values[17]	70	1			T271	1		T866	1		T871	1
values[18]	108	1			T271	1		T866	1		T871	1
values[19]	104	1			T271	1		T866	1		T871	1
values[20]	102	1			T271	1		T866	1		T871	1
values[21]	96	1			T271	1		T866	1		T871	1
values[22]	83	1			T271	1		T866	1		T871	1
values[23]	106	1			T271	1		T866	1		T871	1
values[24]	117	1			T271	1		T866	1		T871	1
values[25]	95	1			T271	1		T866	1		T871	1
values[26]	82	1			T271	1		T866	1		T871	1
values[27]	89	1			T271	1		T866	1		T871	1
values[28]	94	1			T271	1		T866	1		T871	1
values[29]	100	1			T271	1		T866	1		T871	1
values[30]	79	1			T271	1		T866	1		T871	1
values[31]	58	1			T271	1		T866	1		T871	1
values[32]	49	1			T271	1		T866	1		T871	1
values[33]	71	1			T271	1		T866	1		T871	1
values[34]	93	1			T271	1		T866	1		T871	1
values[35]	61	1			T271	1		T866	1		T871	1
values[36]	59	1			T271	1		T866	1		T871	1
values[37]	84	1			T271	1		T866	1		T871	1
values[38]	86	1			T271	1		T866	1		T871	1
values[39]	83	1			T271	1		T866	1		T871	1
values[40]	80	1			T271	1		T866	1		T871	1
values[41]	79	1			T271	1		T866	1		T871	1
values[42]	63	1			T271	1		T866	1		T871	1
values[43]	66	1			T271	1		T866	1		T871	1
values[44]	70	1			T271	1		T866	1		T871	1
values[45]	77	1			T271	1		T866	1		T871	2
values[46]	71	1			T271	1		T866	1		T871	1
values[47]	70	1			T271	1		T866	1		T871	1
values[48]	45	1			T271	1		T866	1		T871	1
values[49]	48	1			T271	1		T866	1		T871	1
values[50]	70	1			T271	1		T866	1		T871	1
values[51]	87	1			T271	1		T866	1		T871	1
values[52]	79	1			T271	1		T866	1		T871	1
values[53]	80	1			T271	1		T866	1		T871	1
values[54]	82	1			T271	1		T866	1		T871	1
values[55]	76	1			T271	1		T866	1		T871	1
values[56]	64	1			T271	1		T866	1		T871	1
values[57]	53	1			T271	1		T866	1		T871	1
values[58]	60	1			T271	1		T866	1		T871	1
values[59]	46	1			T271	1		T866	1		T871	1
values[60]	44	1			T271	1		T866	1		T871	1
values[61]	39	1			T271	1		T866	1		T871	1
values[62]	42	1			T271	1		T866	1		T871	1
values[63]	54	1			T271	1		T866	1		T871	1
values[64]	58	1			T271	1		T866	1		T871	1
values[65]	54	1			T271	1		T866	1		T871	1
values[66]	70	1			T271	1		T866	1		T871	1
values[67]	40	1			T271	1		T866	1		T871	1
values[68]	43	1			T271	1		T866	1		T871	1
values[69]	41	1			T271	1		T866	1		T871	1
values[70]	36	1			T271	1		T866	1		T871	1
values[71]	47	1			T271	1		T866	1		T871	1
values[72]	41	1			T271	1		T866	1		T871	1
values[73]	41	1			T271	1		T866	1		T871	1
values[74]	38	1			T271	1		T866	1		T871	1
values[75]	40	1			T271	1		T866	1		T871	1
values[76]	56	1			T271	1		T866	1		T871	1
values[77]	77	1			T271	1		T866	1		T871	1
values[78]	81	1			T271	1		T866	2		T871	1
values[79]	66	1			T271	1		T866	1		T871	1
values[80]	55	1			T271	1		T866	1		T871	1
values[81]	85	1			T271	1		T866	1		T871	1
values[82]	90	1			T271	1		T866	1		T871	1
values[83]	53	1			T271	1		T866	1		T871	1
values[84]	41	1			T271	1		T866	1		T871	1
values[85]	36	1			T271	1		T866	1		T871	1
values[86]	27	1			T271	1		T866	1		T871	1
values[87]	31	1			T271	1		T866	1		T871	1
values[88]	32	1			T271	5		T866	1		T871	1
values[89]	37	1			T271	2		T866	1		T871	1
values[90]	32	1			T271	4		T866	1		T871	1
values[91]	46	1			T271	4		T866	1		T871	1
values[92]	50	1			T271	7		T866	1		T871	1
values[93]	34	1			T271	4		T866	1		T871	1
values[94]	40	1			T271	3		T866	1		T871	1
values[95]	46	1			T271	5		T866	1		T871	1
values[96]	43	1			T271	3		T866	1		T871	1
values[97]	52	1			T271	3		T866	1		T871	1
values[98]	55	1			T271	1		T866	1		T871	1
values[99]	41	1			T271	1		T866	1		T871	1
values[100]	48	1			T271	1		T866	1		T871	2
values[101]	49	1			T271	4		T866	1		T871	1
values[102]	51	1			T271	3		T866	1		T871	3
values[103]	47	1			T271	6		T866	2		T871	4
values[104]	30	1			T271	4		T866	1		T871	1
values[105]	50	1			T271	1		T866	1		T871	1
values[106]	50	1			T271	3		T866	1		T871	5
values[107]	42	1			T271	1		T866	1		T871	1
values[108]	47	1			T271	2		T866	1		T871	1
values[109]	49	1			T271	3		T866	1		T871	1
values[110]	42	1			T271	2		T866	1		T871	1
values[111]	40	1			T271	1		T866	1		T871	1
values[112]	53	1			T271	1		T866	1		T871	2
values[113]	56	1			T271	3		T866	1		T871	2
values[114]	55	1			T271	1		T866	1		T871	2
values[115]	57	1			T271	1		T866	1		T871	2
values[116]	51	1			T271	1		T866	1		T871	3
values[117]	65	1			T271	1		T866	1		T871	5
values[118]	47	1			T271	3		T866	1		T871	3
values[119]	46	1			T271	3		T866	1		T871	2
values[120]	48	1			T271	4		T866	1		T871	2
values[121]	38	1			T271	1		T866	1		T871	1
values[122]	45	1			T271	2		T866	1		T871	1
values[123]	51	1			T271	2		T866	1		T871	3
values[124]	42	1			T271	1		T866	1		T871	1
values[125]	43	1			T271	1		T866	1		T871	1
values[126]	305	1			T271	8		T866	11		T871	10
values[127]	2603	1			T271	102		T866	116		T871	121
values[128]	5065	1			T271	219		T866	168		T871	245