Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	95.48	94.18	95.43		94.99	96.65	99.51

Total tests in report: 2900

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
44.23	44.23	57.30	57.30	51.19	51.19	28.62	28.62			69.20	69.20	58.92	58.92	0.13	0.13	/workspace/coverage/default/0.chip_plic_all_irqs_0.112796867
54.60	10.38	68.41	11.11	64.25	13.05	31.21	2.60			81.21	12.01	81.99	23.08	0.55	0.42	/workspace/coverage/default/2.chip_jtag_csr_rw.2404180362
60.44	5.84	74.65	6.24	66.46	2.22	33.09	1.87			81.23	0.02	81.99	0.00	25.21	24.66	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3147911828
63.81	3.37	74.65	0.00	66.73	0.26	33.09	0.00			81.30	0.06	81.99	0.00	45.11	19.89	/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.475237270
67.01	3.20	80.48	5.82	70.89	4.16	36.97	3.89			83.28	1.98	85.31	3.32	45.11	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.343484121
69.65	2.64	82.76	2.28	73.65	2.76	45.50	8.53			85.21	1.94	85.66	0.35	45.11	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.817592814
72.24	2.60	82.96	0.21	75.88	2.23	48.32	2.82			85.42	0.20	85.66	0.00	55.22	10.12	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2401230767
74.63	2.39	82.96	0.00	75.88	0.00	48.32	0.00			85.42	0.00	85.66	0.00	69.55	14.32	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1602857796
76.88	2.25	82.96	0.00	75.88	0.00	61.81	13.49			85.42	0.00	85.66	0.00	69.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2443130038
78.47	1.59	83.24	0.27	76.02	0.15	70.07	8.25			85.60	0.18	86.36	0.70	69.56	0.01	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.759179652
79.99	1.51	84.76	1.53	77.31	1.29	71.08	1.02			86.94	1.35	90.21	3.85	69.60	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2915450299
81.29	1.31	85.40	0.64	78.12	0.81	74.18	3.10			87.49	0.55	90.21	0.00	72.34	2.74	/workspace/coverage/default/0.chip_sw_alert_test.622546345
82.42	1.13	85.40	0.00	78.12	0.00	74.18	0.00			87.49	0.00	90.21	0.00	79.11	6.77	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3473079534
83.47	1.05	86.41	1.01	80.41	2.29	74.27	0.09			89.72	2.22	90.91	0.70	79.11	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1565285405
84.46	0.99	86.41	0.00	80.42	0.01	74.27	0.00			89.72	0.00	90.91	0.00	85.02	5.91	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.123582259
85.35	0.89	87.88	1.47	81.64	1.23	76.36	2.09			90.25	0.53	90.91	0.00	85.04	0.02	/workspace/coverage/default/1.chip_jtag_csr_rw.2246964359
86.16	0.81	88.34	0.46	81.86	0.22	76.43	0.07			90.51	0.26	94.76	3.85	85.04	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.597461386
86.90	0.74	88.34	0.00	81.86	0.00	76.43	0.00			90.51	0.00	94.76	0.00	89.48	4.44	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2476346953
87.64	0.74	89.93	1.60	83.13	1.26	77.05	0.61			91.47	0.97	94.76	0.00	89.48	0.00	/workspace/coverage/default/2.chip_sw_gpio.2611254093
88.35	0.71	89.93	0.00	83.13	0.00	81.34	4.29			91.47	0.00	94.76	0.00	89.48	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2808714973
89.01	0.65	89.94	0.01	83.13	0.01	85.25	3.91			91.47	0.00	94.76	0.00	89.48	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2734513304
89.63	0.62	91.07	1.12	84.02	0.89	85.96	0.71			92.49	1.02	94.76	0.00	89.48	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3140670782
90.18	0.55	91.08	0.01	86.84	2.82	85.96	0.00			92.49	0.00	94.76	0.00	89.94	0.46	/workspace/coverage/cover_reg_top/8.chip_tl_errors.3621860386
90.67	0.50	91.64	0.56	88.81	1.97	86.07	0.11			92.66	0.16	94.76	0.00	90.12	0.18	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.479265890
91.11	0.43	91.64	0.00	88.81	0.00	86.07	0.00			92.66	0.00	94.76	0.00	92.73	2.61	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1445671646
91.45	0.34	92.43	0.80	89.05	0.24	86.63	0.56			92.75	0.09	95.10	0.35	92.73	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.840673261
91.76	0.31	92.71	0.28	89.21	0.16	87.92	1.29			92.85	0.11	95.10	0.00	92.76	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1023234633
92.05	0.29	92.71	0.00	89.31	0.10	87.92	0.00			92.87	0.02	95.10	0.00	94.41	1.64	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.339112280
92.32	0.27	93.20	0.49	89.73	0.43	88.20	0.28			93.28	0.41	95.10	0.00	94.41	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2754652763
92.58	0.26	93.20	0.00	89.73	0.00	88.32	0.12			93.28	0.00	95.10	0.00	95.85	1.45	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2765925444
92.83	0.25	93.20	0.00	89.73	0.00	88.32	0.00			93.28	0.00	95.10	0.00	97.33	1.48	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.733047678
93.05	0.22	93.25	0.06	89.90	0.17	89.13	0.80			93.41	0.13	95.28	0.17	97.33	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2418253665
93.26	0.21	93.57	0.32	90.18	0.28	89.54	0.41			93.66	0.25	95.28	0.00	97.34	0.01	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3370854066
93.44	0.18	93.57	0.00	90.18	0.00	90.59	1.06			93.66	0.00	95.28	0.00	97.34	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.526221459
93.60	0.16	93.63	0.06	90.19	0.01	91.45	0.86			93.67	0.01	95.28	0.00	97.34	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.4024521315
93.75	0.15	93.88	0.25	90.51	0.32	91.81	0.35			93.67	0.00	95.28	0.00	97.34	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3516275106
93.88	0.13	93.89	0.01	90.58	0.07	91.88	0.07			93.68	0.01	95.28	0.00	97.97	0.62	/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3974820063
94.01	0.13	93.90	0.01	90.94	0.36	91.88	0.00			94.08	0.41	95.28	0.00	97.97	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3067018775
94.12	0.11	94.08	0.19	90.98	0.05	92.26	0.38			94.11	0.02	95.28	0.00	97.98	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3398343918
94.22	0.10	94.08	0.00	91.58	0.60	92.26	0.00			94.11	0.00	95.28	0.00	97.98	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.728388183
94.32	0.10	94.32	0.23	91.71	0.12	92.38	0.12			94.23	0.12	95.28	0.00	97.98	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.155908691
94.40	0.08	94.32	0.00	91.71	0.00	92.87	0.49			94.23	0.00	95.28	0.00	97.98	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.344484429
94.48	0.08	94.32	0.00	91.71	0.00	93.34	0.47			94.23	0.00	95.28	0.00	97.98	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3755604247
94.55	0.08	94.36	0.04	91.87	0.16	93.38	0.04			94.27	0.04	95.45	0.17	97.98	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.745125493
94.61	0.06	94.36	0.00	92.04	0.17	93.39	0.01			94.47	0.19	95.45	0.00	97.98	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2111994071
94.67	0.06	94.37	0.01	92.04	0.00	93.39	0.01			94.47	0.00	95.80	0.35	97.98	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1132823405
94.73	0.06	94.48	0.11	92.11	0.07	93.50	0.11			94.53	0.06	95.80	0.00	97.98	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.312574247
94.79	0.05	94.48	0.00	92.11	0.00	93.81	0.32			94.53	0.00	95.80	0.00	97.98	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4239008667
94.84	0.05	94.48	0.00	92.35	0.24	93.81	0.00			94.60	0.06	95.80	0.00	97.98	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.4153086924
94.89	0.05	94.48	0.00	92.44	0.08	93.81	0.00			94.61	0.02	95.80	0.00	98.18	0.20	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.31457402
94.93	0.04	94.49	0.01	92.47	0.03	93.82	0.01			94.64	0.02	95.98	0.17	98.19	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2405549360
94.97	0.04	94.51	0.02	92.51	0.04	93.82	0.00			94.65	0.02	96.15	0.17	98.20	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.964443547
95.02	0.04	94.51	0.00	92.51	0.00	94.08	0.26			94.65	0.00	96.15	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3812502967
95.06	0.04	94.51	0.00	92.76	0.25	94.08	0.00			94.65	0.00	96.15	0.00	98.20	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.250904993
95.10	0.04	94.51	0.00	92.78	0.02	94.28	0.20			94.67	0.02	96.15	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.968711035
95.14	0.04	94.52	0.01	92.80	0.01	94.28	0.00			94.69	0.02	96.33	0.17	98.21	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2999382304
95.17	0.04	94.52	0.01	92.81	0.01	94.28	0.01			94.70	0.01	96.50	0.17	98.23	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3607913466
95.21	0.03	94.52	0.00	92.81	0.00	94.47	0.19			94.70	0.00	96.50	0.00	98.23	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3432513858
95.23	0.03	94.52	0.00	92.90	0.10	94.47	0.00			94.73	0.03	96.50	0.00	98.27	0.05	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2522245730
95.26	0.03	94.52	0.00	92.90	0.00	94.47	0.00			94.73	0.00	96.68	0.17	98.27	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3983517378
95.29	0.03	94.59	0.07	92.90	0.00	94.55	0.08			94.74	0.01	96.68	0.00	98.27	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.2917577653
95.32	0.03	94.63	0.03	92.98	0.08	94.55	0.00			94.78	0.04	96.68	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3837135831
95.34	0.03	94.66	0.03	93.03	0.05	94.60	0.05			94.81	0.02	96.68	0.00	98.27	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3686512059
95.37	0.02	94.72	0.06	93.06	0.03	94.61	0.01			94.86	0.05	96.68	0.00	98.27	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2631077032
95.39	0.02	94.73	0.01	93.07	0.01	94.72	0.11			94.86	0.01	96.68	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.1928977535
95.41	0.02	94.73	0.00	93.18	0.11	94.72	0.00			94.86	0.00	96.68	0.00	98.28	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3019917074
95.43	0.02	94.73	0.00	93.29	0.12	94.72	0.00			94.86	0.00	96.68	0.00	98.28	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3224526891
95.45	0.02	94.73	0.00	93.30	0.01	94.72	0.00			94.86	0.00	96.68	0.00	98.39	0.11	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2075938536
95.47	0.02	94.75	0.02	93.32	0.02	94.75	0.03			94.90	0.03	96.68	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3885819960
95.48	0.02	94.76	0.01	93.35	0.03	94.80	0.05			94.91	0.02	96.68	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.307888661
95.50	0.02	94.76	0.00	93.39	0.04	94.80	0.00			94.91	0.00	96.68	0.00	98.45	0.06	/workspace/coverage/cover_reg_top/10.xbar_stress_all.1139472986
95.51	0.01	94.76	0.00	93.40	0.01	94.80	0.00			94.91	0.00	96.68	0.00	98.53	0.08	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3985714977
95.53	0.01	94.76	0.00	93.40	0.00	94.89	0.09			94.91	0.00	96.68	0.00	98.53	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2946412850
95.54	0.01	94.76	0.00	93.47	0.07	94.89	0.00			94.91	0.00	96.68	0.00	98.53	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1595251831
95.55	0.01	94.76	0.00	93.47	0.00	94.96	0.07			94.91	0.00	96.68	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3773163729
95.56	0.01	94.76	0.00	93.53	0.05	94.96	0.00			94.93	0.02	96.68	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all.2851429527
95.58	0.01	94.76	0.00	93.53	0.01	94.96	0.00			94.93	0.00	96.68	0.00	98.59	0.06	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3087236355
95.59	0.01	94.79	0.02	93.53	0.00	95.00	0.04			94.93	0.00	96.68	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3623443552
95.60	0.01	94.82	0.03	93.56	0.02	95.00	0.00			94.94	0.01	96.68	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1278245782
95.61	0.01	94.82	0.00	93.62	0.06	95.00	0.00			94.94	0.00	96.68	0.00	98.59	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3798893917
95.62	0.01	94.82	0.00	93.67	0.05	95.00	0.00			94.94	0.00	96.68	0.00	98.60	0.01	/workspace/coverage/cover_reg_top/7.chip_tl_errors.972028932
95.63	0.01	94.82	0.00	93.67	0.01	95.00	0.00			94.94	0.00	96.68	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.817514419
95.63	0.01	94.85	0.02	93.68	0.01	95.00	0.01			94.95	0.02	96.68	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4146611140
95.64	0.01	94.85	0.00	93.69	0.01	95.00	0.00			94.95	0.00	96.68	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1312798772
95.65	0.01	94.87	0.02	93.69	0.01	95.00	0.01			94.96	0.01	96.68	0.00	98.70	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2247416184
95.66	0.01	94.87	0.00	93.74	0.05	95.00	0.00			94.96	0.00	96.68	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.481354527
95.66	0.01	94.87	0.00	93.79	0.05	95.00	0.00			94.96	0.00	96.68	0.00	98.70	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2345965664
95.67	0.01	94.87	0.01	93.81	0.02	95.02	0.02			94.96	0.00	96.68	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2654430256
95.68	0.01	94.87	0.00	93.81	0.00	95.06	0.04			94.96	0.00	96.68	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1439554009
95.69	0.01	94.87	0.00	93.81	0.00	95.10	0.04			94.96	0.00	96.68	0.00	98.70	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3597700260
95.69	0.01	94.87	0.00	93.81	0.00	95.14	0.04			94.96	0.00	96.68	0.00	98.70	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.664822465
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95.72	0.01	94.88	0.00	93.82	0.01	95.24	0.01			94.96	0.00	96.68	0.00	98.74	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2938410547
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95.73	0.01	94.88	0.00	93.85	0.00	95.27	0.03			94.96	0.00	96.68	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.71120492
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95.75	0.01	94.88	0.00	93.94	0.02	95.27	0.00			94.96	0.00	96.68	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all.2520258981
95.75	0.01	94.88	0.00	93.97	0.02	95.27	0.00			94.96	0.00	96.68	0.00	98.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2213947063
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95.76	0.01	94.88	0.00	93.98	0.01	95.27	0.00			94.98	0.02	96.68	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.529565329
95.76	0.01	94.88	0.00	93.98	0.00	95.29	0.02			94.98	0.00	96.68	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.24211502
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95.77	0.01	94.88	0.01	94.01	0.00	95.31	0.01			94.98	0.00	96.68	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2149135872
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95.78	0.01	94.88	0.00	94.04	0.01	95.31	0.00			94.98	0.00	96.68	0.00	98.77	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.815964250
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95.78	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.768243552
95.79	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3311055191
95.79	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2444996465
95.79	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.83	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.809224677
95.79	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.84	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703968153
95.79	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.85	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.302866895
95.80	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.86	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.574377349
95.80	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.87	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2026515166
95.80	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.88	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.630342852
95.80	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.90	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2242316906
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95.81	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.92	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765754472
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95.81	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.94	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2895713340
95.81	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.95	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4238478260
95.81	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.97	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3470629536
95.82	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.98	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1069347971
95.82	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	98.99	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.81891204
95.82	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.00	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3440457273
95.82	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.01	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.733458346
95.82	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.02	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.346521997
95.83	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.04	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092824400
95.83	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.05	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3488050616
95.83	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.06	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.4042040616
95.83	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.07	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3230487507
95.83	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.08	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3919132026
95.84	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.10	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2629615257
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95.84	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.12	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2858605743
95.84	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.13	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997848883
95.84	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.14	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189582800
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95.85	0.01	94.88	0.00	94.04	0.00	95.33	0.00			94.98	0.00	96.68	0.00	99.17	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566136593
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95.91	0.01	94.88	0.00	94.04	0.00	95.34	0.01			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1021731301
95.91	0.01	94.88	0.00	94.04	0.00	95.35	0.01			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.2558577563
95.91	0.01	94.88	0.00	94.05	0.01	95.35	0.00			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.3684093857
95.91	0.01	94.88	0.00	94.06	0.01	95.35	0.00			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.520987122
95.91	0.01	94.88	0.00	94.08	0.01	95.35	0.00			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3113817438
95.92	0.01	94.88	0.00	94.09	0.01	95.35	0.00			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_gpio.1389769834
95.92	0.01	94.88	0.00	94.10	0.01	95.35	0.00			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1660598748
95.92	0.01	94.89	0.01	94.10	0.00	95.36	0.01			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_all_escalation_resets.728344111
95.92	0.01	94.89	0.00	94.10	0.00	95.37	0.01			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.590277720
95.92	0.01	94.89	0.00	94.10	0.00	95.38	0.01			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.981599117
95.92	0.01	94.89	0.00	94.10	0.00	95.39	0.01			94.98	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2060594581
95.92	0.01	94.89	0.00	94.10	0.00	95.39	0.00			94.99	0.01	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1894121603
95.93	0.01	94.89	0.00	94.10	0.01	95.39	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4002076752
95.93	0.01	94.89	0.00	94.11	0.01	95.39	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all.1661952792
95.93	0.01	94.89	0.00	94.12	0.01	95.39	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3521414950
95.93	0.01	94.89	0.00	94.12	0.00	95.39	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3627679066
95.93	0.01	94.89	0.00	94.12	0.00	95.40	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2609215339
95.93	0.01	94.89	0.00	94.12	0.00	95.41	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.538340006
95.93	0.01	94.89	0.01	94.12	0.01	95.41	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3147032801
95.93	0.01	94.90	0.01	94.12	0.00	95.41	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.251779738
95.93	0.01	94.90	0.00	94.12	0.00	95.41	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/34.xbar_same_source.1377543001
95.94	0.01	94.90	0.00	94.12	0.00	95.42	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3020041943
95.94	0.01	94.90	0.00	94.12	0.00	95.42	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2194859240
95.94	0.01	94.90	0.00	94.12	0.00	95.43	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1856985424
95.94	0.01	94.90	0.00	94.12	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3012020135
95.94	0.01	94.90	0.00	94.13	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2337470564
95.94	0.01	94.90	0.00	94.13	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.1884864730
95.94	0.01	94.90	0.00	94.14	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3776918160
95.94	0.01	94.90	0.00	94.14	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/28.xbar_error_random.2479573200
95.94	0.01	94.90	0.00	94.14	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1142387915
95.94	0.01	94.90	0.00	94.15	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1545850228
95.94	0.01	94.90	0.00	94.15	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.4214283796
95.94	0.01	94.90	0.00	94.15	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1124171123
95.94	0.01	94.90	0.00	94.16	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.454672861
95.94	0.01	94.90	0.00	94.16	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2878068139
95.94	0.01	94.90	0.00	94.16	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.540685799
95.94	0.01	94.90	0.00	94.17	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.633924452
95.95	0.01	94.90	0.00	94.17	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3151046191
95.95	0.01	94.90	0.00	94.17	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1760847368
95.95	0.01	94.90	0.00	94.18	0.01	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3367468374
95.95	0.01	94.90	0.00	94.18	0.00	95.43	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1091790473
95.95	0.01	94.90	0.01	94.18	0.00	95.43	0.00			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.352417812
95.95	0.01	94.90	0.00	94.18	0.00	95.43	0.01			94.99	0.00	96.68	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.96424840

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.361253230
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2718782988
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.560504745
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3473479167
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2106816443
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3184724471
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1041042376
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2385924298
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2668013643
/workspace/coverage/cover_reg_top/0.xbar_error_random.234432794
/workspace/coverage/cover_reg_top/0.xbar_random.1326687453
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3355197774
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2726885317
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1116426215
/workspace/coverage/cover_reg_top/0.xbar_same_source.2551148270
/workspace/coverage/cover_reg_top/0.xbar_smoke.1213028609
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1850338069
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2168879628
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3764947323
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3970719696
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1816594143
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2977533206
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2570895896
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2013796905
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2266995197
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2399779308
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1294398316
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2486737120
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3372157552
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3544661748
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3833683950
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2769083001
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2745285350
/workspace/coverage/cover_reg_top/1.xbar_error_random.3078702931
/workspace/coverage/cover_reg_top/1.xbar_random.175609237
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1917120289
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.586130903
/workspace/coverage/cover_reg_top/1.xbar_same_source.2282467056
/workspace/coverage/cover_reg_top/1.xbar_smoke.3369473133
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.444018044
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.157914993
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3360735427
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1323917649
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2537297414
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2589214813
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.37470289
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1545080374
/workspace/coverage/cover_reg_top/10.chip_csr_rw.185614696
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2524123117
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3315981929
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2326156445
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.568189112
/workspace/coverage/cover_reg_top/10.xbar_error_random.2867607976
/workspace/coverage/cover_reg_top/10.xbar_random.2567644401
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2539877403
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1305981054
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2766833100
/workspace/coverage/cover_reg_top/10.xbar_same_source.2836930525
/workspace/coverage/cover_reg_top/10.xbar_smoke.3548662734
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3110437956
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2437249422
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1720917607
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3234172544
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.497109360
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.544659559
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2711266788
/workspace/coverage/cover_reg_top/11.chip_csr_rw.979471509
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2912231315
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2318838048
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1600494383
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3353464750
/workspace/coverage/cover_reg_top/11.xbar_error_random.1825311882
/workspace/coverage/cover_reg_top/11.xbar_random.1069362927
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3802924655
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3341564000
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.281249298
/workspace/coverage/cover_reg_top/11.xbar_same_source.403759244
/workspace/coverage/cover_reg_top/11.xbar_smoke.2297152694
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1564468715
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4195933012
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.356287819
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1062480175
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1587525134
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4005012580
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2070933266
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3886597638
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3971810729
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3204022067
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3056115200
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3066844367
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3877492585
/workspace/coverage/cover_reg_top/12.xbar_error_random.4017260697
/workspace/coverage/cover_reg_top/12.xbar_random.3227424077
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1214666261
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.4007948163
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1484529513
/workspace/coverage/cover_reg_top/12.xbar_same_source.2442960312
/workspace/coverage/cover_reg_top/12.xbar_smoke.1058413398
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3442975974
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2686007813
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2981417986
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3983736284
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3965350402
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4134407665
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2906782001
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2986249353
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3597406423
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.594614167
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3052624226
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2623315678
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3275257771
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1438527299
/workspace/coverage/cover_reg_top/13.xbar_error_random.2699904123
/workspace/coverage/cover_reg_top/13.xbar_random.3623299769
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1326325655
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2035869050
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.995192848
/workspace/coverage/cover_reg_top/13.xbar_same_source.3575807521
/workspace/coverage/cover_reg_top/13.xbar_smoke.4055526957
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1822408994
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.314950147
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2387093115
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2047884876
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3366047306
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1295035169
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.552841529
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2668297500
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2254511095
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2516539672
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1403274352
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1013225009
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.156373625
/workspace/coverage/cover_reg_top/14.xbar_error_random.1990676368
/workspace/coverage/cover_reg_top/14.xbar_random.3683863069
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3170931041
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.723722905
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1520143811
/workspace/coverage/cover_reg_top/14.xbar_same_source.1406524650
/workspace/coverage/cover_reg_top/14.xbar_smoke.2451687399
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2729439499
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1313348961
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/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3055760471
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3145912260
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.686010401
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.983887428
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1341819428
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3620313594
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1189973840
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2646071909
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1567620249
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2118460003
/workspace/coverage/default/4.chip_tap_straps_dev.3250743547
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/workspace/coverage/default/4.chip_tap_straps_rma.3533098904
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3395800489
/workspace/coverage/default/40.chip_sw_all_escalation_resets.229638234
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/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3740816544
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596169554
/workspace/coverage/default/43.chip_sw_all_escalation_resets.587046122
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649819756
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1110706843
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416247366
/workspace/coverage/default/45.chip_sw_all_escalation_resets.4157413542
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/workspace/coverage/default/47.chip_sw_all_escalation_resets.79378079
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1133559703
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.59150389
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1535733921
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.402714845
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3136910477
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942440905
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2032353884
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.740308640
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.399685246
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2412666280
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896045604
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2218436152
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3660838364
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1055538827
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3836708736
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1580016124
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2491331517
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3114964376
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.264586480
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3078735413
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3300899779
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2239589389
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4009847976
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.956331775
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2808372845
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2549851406
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1959073008
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.162598084
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1763315116
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888610529
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1230860113
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3225648397
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3171245667
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3429581672
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2177242407
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3585105964
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142998623
/workspace/coverage/default/67.chip_sw_all_escalation_resets.984564591
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980919391
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2243492404
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.557261316
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2309968434
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.352124235
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3222208987
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2356597023
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3638128458
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4198764036
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3324325445
/workspace/coverage/default/70.chip_sw_all_escalation_resets.573923497
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248235196
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3333070976
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2823760019
/workspace/coverage/default/72.chip_sw_all_escalation_resets.4246054415
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345885938
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1993676442
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020554445
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1553044548
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4162335947
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2934521109
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2491904474
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3217987560
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2477627728
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1635469830
/workspace/coverage/default/78.chip_sw_all_escalation_resets.483833089
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016917570
/workspace/coverage/default/79.chip_sw_all_escalation_resets.429709735
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736319750
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2791995
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.817918342
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3007009029
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382675901
/workspace/coverage/default/80.chip_sw_all_escalation_resets.503610602
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392380881
/workspace/coverage/default/81.chip_sw_all_escalation_resets.585182338
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545081704
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3760310770
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1826877382
/workspace/coverage/default/83.chip_sw_all_escalation_resets.788177230
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680251372
/workspace/coverage/default/84.chip_sw_all_escalation_resets.680210269
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.304866209
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463965403
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2974574948
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.377915243
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3309276481
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3827112044
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4009518492
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2662343029
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3513830972
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1953379609
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1159265714
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3462809815
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2806750891
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1497256070
/workspace/coverage/default/92.chip_sw_all_escalation_resets.268003809
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3802031784
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2344745664
/workspace/coverage/default/95.chip_sw_all_escalation_resets.4226805924
/workspace/coverage/default/96.chip_sw_all_escalation_resets.514931558
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1997398656
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.84010719
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2049875172
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1435197417
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1287765127
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1737892983
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.297530578
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1506402896
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3771888586

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Total test records in report: 2900

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3871046809			Jun 10 08:31:16 PM PDT 24	Jun 10 09:35:26 PM PDT 24	25492897125 ps
T5	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2938410547			Jun 10 08:46:47 PM PDT 24	Jun 10 08:57:52 PM PDT 24	5302490010 ps
T6	/workspace/coverage/default/0.chip_plic_all_irqs_0.112796867			Jun 10 08:21:00 PM PDT 24	Jun 10 08:43:03 PM PDT 24	6174345542 ps
T17	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.504939653			Jun 10 08:25:44 PM PDT 24	Jun 10 09:57:33 PM PDT 24	21801930397 ps
T86	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4118134399			Jun 10 08:30:50 PM PDT 24	Jun 10 08:35:06 PM PDT 24	2871112184 ps
T53	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.817592814			Jun 10 08:29:30 PM PDT 24	Jun 10 10:05:26 PM PDT 24	23185530680 ps
T42	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3398343918			Jun 10 08:47:13 PM PDT 24	Jun 10 08:57:57 PM PDT 24	4659527480 ps
T18	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.759179652			Jun 10 08:46:02 PM PDT 24	Jun 10 08:53:23 PM PDT 24	5161453716 ps
T54	/workspace/coverage/default/0.rom_e2e_asm_init_dev.3722357759			Jun 10 08:27:09 PM PDT 24	Jun 10 09:16:46 PM PDT 24	13969043183 ps
T19	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1987291345			Jun 10 08:29:46 PM PDT 24	Jun 10 09:41:14 PM PDT 24	17691363748 ps
T156	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4200875604			Jun 10 08:17:16 PM PDT 24	Jun 10 08:21:12 PM PDT 24	2445663524 ps
T57	/workspace/coverage/default/1.rom_volatile_raw_unlock.2781357310			Jun 10 08:34:52 PM PDT 24	Jun 10 08:36:46 PM PDT 24	2680141136 ps
T168	/workspace/coverage/default/2.chip_sival_flash_info_access.727953619			Jun 10 08:33:38 PM PDT 24	Jun 10 08:40:02 PM PDT 24	3059394864 ps
T43	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.840673261			Jun 10 08:37:58 PM PDT 24	Jun 10 08:44:40 PM PDT 24	3696003216 ps
T115	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3441888739			Jun 10 08:37:53 PM PDT 24	Jun 10 08:42:46 PM PDT 24	2830196949 ps
T29	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.307888661			Jun 10 08:19:36 PM PDT 24	Jun 10 08:28:01 PM PDT 24	3402072680 ps
T248	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189582800			Jun 10 08:49:09 PM PDT 24	Jun 10 08:56:01 PM PDT 24	3921647612 ps
T169	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3360934812			Jun 10 08:22:31 PM PDT 24	Jun 10 08:29:47 PM PDT 24	3702179104 ps
T712	/workspace/coverage/default/1.chip_sw_csrng_kat_test.2341599078			Jun 10 08:28:27 PM PDT 24	Jun 10 08:32:06 PM PDT 24	3045503972 ps
T753	/workspace/coverage/default/0.chip_sw_hmac_multistream.538166420			Jun 10 08:18:46 PM PDT 24	Jun 10 08:44:53 PM PDT 24	7047277536 ps
T188	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.968711035			Jun 10 08:38:43 PM PDT 24	Jun 10 08:58:26 PM PDT 24	8423563430 ps
T461	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.190032552			Jun 10 08:30:57 PM PDT 24	Jun 10 08:49:02 PM PDT 24	7556015390 ps
T125	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.532783575			Jun 10 08:19:49 PM PDT 24	Jun 10 08:30:23 PM PDT 24	6648767436 ps
T126	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3606634731			Jun 10 08:34:36 PM PDT 24	Jun 10 08:46:32 PM PDT 24	9664423744 ps
T116	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2418253665			Jun 10 08:39:54 PM PDT 24	Jun 10 08:48:10 PM PDT 24	5222215772 ps
T308	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3056739673			Jun 10 08:41:31 PM PDT 24	Jun 10 08:45:48 PM PDT 24	3419034586 ps
T309	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2139909670			Jun 10 08:20:57 PM PDT 24	Jun 10 08:26:06 PM PDT 24	2953123652 ps
T172	/workspace/coverage/default/1.rom_e2e_smoke.1123883218			Jun 10 08:38:50 PM PDT 24	Jun 10 09:39:11 PM PDT 24	14596589496 ps
T64	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1372603224			Jun 10 08:48:02 PM PDT 24	Jun 10 08:57:44 PM PDT 24	5367904800 ps
T310	/workspace/coverage/default/1.chip_sw_hmac_oneshot.3368623164			Jun 10 08:27:27 PM PDT 24	Jun 10 08:32:35 PM PDT 24	2455584584 ps
T311	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3740816544			Jun 10 08:48:55 PM PDT 24	Jun 10 08:54:54 PM PDT 24	3694842486 ps
T181	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.597461386			Jun 10 08:40:12 PM PDT 24	Jun 10 08:44:27 PM PDT 24	2658535004 ps
T23	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3623443552			Jun 10 08:18:49 PM PDT 24	Jun 10 08:32:28 PM PDT 24	6972181817 ps
T59	/workspace/coverage/default/0.chip_sw_alert_test.622546345			Jun 10 08:19:15 PM PDT 24	Jun 10 08:24:47 PM PDT 24	3012203250 ps
T213	/workspace/coverage/default/0.chip_sw_pattgen_ios.251779738			Jun 10 08:17:53 PM PDT 24	Jun 10 08:22:09 PM PDT 24	3049947820 ps
T334	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3919132026			Jun 10 08:47:27 PM PDT 24	Jun 10 08:59:44 PM PDT 24	5926052020 ps
T249	/workspace/coverage/default/2.chip_sw_plic_sw_irq.2529472298			Jun 10 08:37:55 PM PDT 24	Jun 10 08:43:11 PM PDT 24	2832842548 ps
T58	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3406188795			Jun 10 08:29:21 PM PDT 24	Jun 10 08:37:09 PM PDT 24	4627080500 ps
T335	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3739664835			Jun 10 08:36:32 PM PDT 24	Jun 10 08:54:33 PM PDT 24	5947754750 ps
T113	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2734513304			Jun 10 08:21:14 PM PDT 24	Jun 10 08:44:30 PM PDT 24	7800287124 ps
T336	/workspace/coverage/default/2.chip_sw_hmac_oneshot.4144746593			Jun 10 08:38:19 PM PDT 24	Jun 10 08:43:44 PM PDT 24	3594139518 ps
T382	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2999382304			Jun 10 08:47:11 PM PDT 24	Jun 10 08:53:33 PM PDT 24	3991822440 ps
T130	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4239008667			Jun 10 08:19:41 PM PDT 24	Jun 10 09:36:24 PM PDT 24	22023710800 ps
T82	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1023234633			Jun 10 08:18:20 PM PDT 24	Jun 10 08:41:29 PM PDT 24	12082822560 ps
T211	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2661461710			Jun 10 08:36:31 PM PDT 24	Jun 10 08:47:52 PM PDT 24	4033514200 ps
T55	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3432513858			Jun 10 08:18:42 PM PDT 24	Jun 10 08:21:56 PM PDT 24	3209242472 ps
T389	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869283785			Jun 10 08:47:49 PM PDT 24	Jun 10 08:54:50 PM PDT 24	4523437060 ps
T26	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4284452876			Jun 10 08:25:27 PM PDT 24	Jun 10 08:35:49 PM PDT 24	4562276660 ps
T390	/workspace/coverage/default/0.chip_sw_csrng_smoketest.2650058298			Jun 10 08:23:51 PM PDT 24	Jun 10 08:28:02 PM PDT 24	3191816000 ps
T391	/workspace/coverage/default/1.chip_sw_aes_masking_off.3296292377			Jun 10 08:31:25 PM PDT 24	Jun 10 08:36:12 PM PDT 24	3099550907 ps
T56	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1894121603			Jun 10 08:21:35 PM PDT 24	Jun 10 08:29:53 PM PDT 24	5904762975 ps
T264	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1579624655			Jun 10 08:19:25 PM PDT 24	Jun 10 08:28:19 PM PDT 24	3066452814 ps
T131	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.573171142			Jun 10 08:21:14 PM PDT 24	Jun 10 08:28:45 PM PDT 24	6816056752 ps
T220	/workspace/coverage/default/20.chip_sw_all_escalation_resets.81891204			Jun 10 08:45:09 PM PDT 24	Jun 10 08:54:54 PM PDT 24	6590175664 ps
T276	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.4168842357			Jun 10 08:33:12 PM PDT 24	Jun 10 08:36:59 PM PDT 24	2602913268 ps
T277	/workspace/coverage/default/2.chip_sw_aon_timer_irq.4247919558			Jun 10 08:35:31 PM PDT 24	Jun 10 08:44:47 PM PDT 24	3567267544 ps
T221	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.757604750			Jun 10 08:36:09 PM PDT 24	Jun 10 09:29:23 PM PDT 24	14693637100 ps
T63	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.526221459			Jun 10 08:34:28 PM PDT 24	Jun 10 09:52:22 PM PDT 24	43213376915 ps
T27	/workspace/coverage/default/2.chip_sw_gpio_smoketest.79680620			Jun 10 08:41:08 PM PDT 24	Jun 10 08:46:11 PM PDT 24	3081432434 ps
T269	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2491331517			Jun 10 08:48:16 PM PDT 24	Jun 10 08:52:44 PM PDT 24	3675678544 ps
T325	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3668324317			Jun 10 08:25:21 PM PDT 24	Jun 10 08:28:47 PM PDT 24	2759269408 ps
T326	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1739026294			Jun 10 08:36:20 PM PDT 24	Jun 10 08:45:52 PM PDT 24	5095427880 ps
T327	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3225648397			Jun 10 08:49:55 PM PDT 24	Jun 10 08:55:36 PM PDT 24	3634196890 ps
T328	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980919391			Jun 10 08:50:11 PM PDT 24	Jun 10 08:56:19 PM PDT 24	3371653048 ps
T108	/workspace/coverage/default/1.chip_sw_power_sleep_load.1928977535			Jun 10 08:31:27 PM PDT 24	Jun 10 08:45:49 PM PDT 24	10664718744 ps
T329	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2757146186			Jun 10 08:27:26 PM PDT 24	Jun 10 09:22:38 PM PDT 24	14097247520 ps
T330	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.390879841			Jun 10 08:20:59 PM PDT 24	Jun 10 08:41:11 PM PDT 24	6435351801 ps
T71	/workspace/coverage/default/2.chip_tap_straps_dev.3290784278			Jun 10 08:38:39 PM PDT 24	Jun 10 08:53:04 PM PDT 24	8110041745 ps
T144	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4199919689			Jun 10 08:29:22 PM PDT 24	Jun 10 08:34:56 PM PDT 24	3414075090 ps
T377	/workspace/coverage/default/95.chip_sw_all_escalation_resets.4226805924			Jun 10 08:52:12 PM PDT 24	Jun 10 09:00:21 PM PDT 24	5882919376 ps
T402	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3977751138			Jun 10 08:20:49 PM PDT 24	Jun 10 08:25:53 PM PDT 24	2820749500 ps
T931	/workspace/coverage/default/0.chip_sw_example_flash.887244323			Jun 10 08:16:53 PM PDT 24	Jun 10 08:19:52 PM PDT 24	2210389344 ps
T363	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.367590728			Jun 10 08:30:13 PM PDT 24	Jun 10 08:41:12 PM PDT 24	4523267753 ps
T68	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.4024521315			Jun 10 08:21:37 PM PDT 24	Jun 10 09:08:34 PM PDT 24	13031947664 ps
T374	/workspace/coverage/default/2.chip_sw_hmac_enc.1797324928			Jun 10 08:36:53 PM PDT 24	Jun 10 08:40:34 PM PDT 24	2233175876 ps
T52	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1795598040			Jun 10 08:29:06 PM PDT 24	Jun 10 09:15:38 PM PDT 24	10587020200 ps
T127	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1088419830			Jun 10 08:27:31 PM PDT 24	Jun 10 08:56:04 PM PDT 24	8592361552 ps
T731	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3455864007			Jun 10 08:25:19 PM PDT 24	Jun 10 09:19:43 PM PDT 24	14933291336 ps
T118	/workspace/coverage/default/0.rom_volatile_raw_unlock.3445242495			Jun 10 08:23:14 PM PDT 24	Jun 10 08:25:03 PM PDT 24	2396962233 ps
T117	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.647172362			Jun 10 08:20:26 PM PDT 24	Jun 10 08:56:51 PM PDT 24	11380042672 ps
T145	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3386957221			Jun 10 08:37:20 PM PDT 24	Jun 10 08:40:54 PM PDT 24	2458323593 ps
T128	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3755604247			Jun 10 08:39:25 PM PDT 24	Jun 10 08:50:24 PM PDT 24	6020766000 ps
T932	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1674131948			Jun 10 08:20:32 PM PDT 24	Jun 10 08:24:22 PM PDT 24	3013908559 ps
T376	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1497256070			Jun 10 08:50:52 PM PDT 24	Jun 10 08:58:58 PM PDT 24	4477614940 ps
T121	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1772343167			Jun 10 08:41:03 PM PDT 24	Jun 10 08:52:10 PM PDT 24	5140559232 ps
T46	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2800256160			Jun 10 08:20:04 PM PDT 24	Jun 10 08:28:49 PM PDT 24	5519727516 ps
T933	/workspace/coverage/default/1.chip_sw_hmac_multistream.2343281357			Jun 10 08:26:41 PM PDT 24	Jun 10 08:54:29 PM PDT 24	6739234456 ps
T287	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.664822465			Jun 10 08:29:36 PM PDT 24	Jun 10 10:06:23 PM PDT 24	21889886558 ps
T129	/workspace/coverage/default/1.chip_sw_edn_kat.2852237846			Jun 10 08:28:46 PM PDT 24	Jun 10 08:40:13 PM PDT 24	3194249616 ps
T934	/workspace/coverage/default/0.chip_sw_aes_idle.2575290305			Jun 10 08:20:10 PM PDT 24	Jun 10 08:24:35 PM PDT 24	3442278696 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2915450299			Jun 10 08:20:23 PM PDT 24	Jun 10 08:28:11 PM PDT 24	7605780656 ps
T100	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4009518492			Jun 10 08:53:20 PM PDT 24	Jun 10 08:59:39 PM PDT 24	3582057052 ps
T101	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2394338927			Jun 10 08:38:08 PM PDT 24	Jun 10 08:59:48 PM PDT 24	5095469144 ps
T102	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3477115621			Jun 10 08:40:23 PM PDT 24	Jun 10 09:09:45 PM PDT 24	11508606492 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2727212891			Jun 10 08:44:30 PM PDT 24	Jun 10 08:52:36 PM PDT 24	7640230812 ps
T103	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1272091278			Jun 10 08:24:32 PM PDT 24	Jun 10 08:40:49 PM PDT 24	6029911672 ps
T104	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1179645611			Jun 10 08:26:18 PM PDT 24	Jun 10 08:38:37 PM PDT 24	6526899784 ps
T105	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3651936871			Jun 10 08:25:06 PM PDT 24	Jun 10 10:01:59 PM PDT 24	22551024428 ps
T106	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1826877382			Jun 10 08:50:29 PM PDT 24	Jun 10 08:58:08 PM PDT 24	3660091160 ps
T107	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3923746435			Jun 10 08:36:05 PM PDT 24	Jun 10 09:31:15 PM PDT 24	13860768890 ps
T935	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.305637803			Jun 10 08:27:34 PM PDT 24	Jun 10 08:39:02 PM PDT 24	5003050296 ps
T147	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3370854066			Jun 10 08:16:51 PM PDT 24	Jun 10 11:58:50 PM PDT 24	77528705514 ps
T176	/workspace/coverage/default/0.rom_e2e_shutdown_output.284586565			Jun 10 08:27:13 PM PDT 24	Jun 10 09:25:48 PM PDT 24	23286072136 ps
T72	/workspace/coverage/default/1.chip_tap_straps_prod.1088774504			Jun 10 08:28:28 PM PDT 24	Jun 10 08:39:42 PM PDT 24	6182522344 ps
T352	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.352417812			Jun 10 08:19:32 PM PDT 24	Jun 10 08:36:16 PM PDT 24	4812837340 ps
T219	/workspace/coverage/default/0.chip_tap_straps_dev.2864313440			Jun 10 08:19:23 PM PDT 24	Jun 10 08:22:19 PM PDT 24	2982824962 ps
T936	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2060594581			Jun 10 08:39:36 PM PDT 24	Jun 10 08:45:25 PM PDT 24	2877767186 ps
T737	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1255876007			Jun 10 08:29:12 PM PDT 24	Jun 10 08:48:54 PM PDT 24	7614651222 ps
T218	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1233555196			Jun 10 08:24:38 PM PDT 24	Jun 10 08:46:07 PM PDT 24	7911383344 ps
T937	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1455569050			Jun 10 08:38:53 PM PDT 24	Jun 10 08:43:22 PM PDT 24	3105431664 ps
T778	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1501998837			Jun 10 08:43:42 PM PDT 24	Jun 10 08:51:11 PM PDT 24	4185411592 ps
T938	/workspace/coverage/default/2.chip_sw_edn_kat.1970331507			Jun 10 08:36:37 PM PDT 24	Jun 10 08:48:02 PM PDT 24	3661744368 ps
T709	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1958465853			Jun 10 08:36:54 PM PDT 24	Jun 10 09:01:12 PM PDT 24	6586666036 ps
T475	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.105739271			Jun 10 08:24:25 PM PDT 24	Jun 10 08:36:59 PM PDT 24	9185665380 ps
T224	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4036844440			Jun 10 08:23:57 PM PDT 24	Jun 10 08:49:13 PM PDT 24	6755284804 ps
T122	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3928101015			Jun 10 08:33:03 PM PDT 24	Jun 10 08:42:48 PM PDT 24	3553977609 ps
T939	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.643849855			Jun 10 08:25:30 PM PDT 24	Jun 10 08:30:04 PM PDT 24	2387524852 ps
T940	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3825564138			Jun 10 08:36:36 PM PDT 24	Jun 10 08:54:09 PM PDT 24	5345579030 ps
T398	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2823760019			Jun 10 08:50:37 PM PDT 24	Jun 10 08:57:52 PM PDT 24	4073989952 ps
T941	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1629994954			Jun 10 08:29:42 PM PDT 24	Jun 10 08:37:50 PM PDT 24	4049125358 ps
T399	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.597889868			Jun 10 08:47:19 PM PDT 24	Jun 10 08:54:21 PM PDT 24	3710665676 ps
T339	/workspace/coverage/default/11.chip_sw_all_escalation_resets.302866895			Jun 10 08:45:42 PM PDT 24	Jun 10 08:55:56 PM PDT 24	4706967360 ps
T467	/workspace/coverage/default/1.chip_sw_otbn_randomness.2054055769			Jun 10 08:29:12 PM PDT 24	Jun 10 08:48:09 PM PDT 24	5911807412 ps
T771	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.4027183203			Jun 10 08:23:25 PM PDT 24	Jun 10 08:32:51 PM PDT 24	5571016465 ps
T49	/workspace/coverage/default/2.chip_sw_spi_device_tpm.3024222322			Jun 10 08:35:04 PM PDT 24	Jun 10 08:41:41 PM PDT 24	3376913284 ps
T464	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3893506815			Jun 10 08:31:55 PM PDT 24	Jun 10 08:36:15 PM PDT 24	3001845948 ps
T404	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2957700336			Jun 10 08:30:08 PM PDT 24	Jun 10 08:33:25 PM PDT 24	2942173170 ps
T65	/workspace/coverage/default/3.chip_tap_straps_rma.2917577653			Jun 10 08:43:09 PM PDT 24	Jun 10 08:46:01 PM PDT 24	3042056916 ps
T212	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.962110106			Jun 10 08:33:21 PM PDT 24	Jun 10 08:45:53 PM PDT 24	3906987480 ps
T463	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1810574184			Jun 10 08:33:27 PM PDT 24	Jun 10 08:43:02 PM PDT 24	4502253008 ps
T178	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3646650788			Jun 10 08:36:10 PM PDT 24	Jun 10 09:29:23 PM PDT 24	14388348357 ps
T942	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.822713814			Jun 10 08:40:06 PM PDT 24	Jun 10 08:44:44 PM PDT 24	3452865529 ps
T152	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2091239203			Jun 10 08:27:21 PM PDT 24	Jun 10 08:52:01 PM PDT 24	8284168600 ps
T353	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1336352236			Jun 10 08:20:38 PM PDT 24	Jun 10 08:24:01 PM PDT 24	2503772728 ps
T30	/workspace/coverage/default/0.chip_sw_usbdev_stream.1856048291			Jun 10 08:17:15 PM PDT 24	Jun 10 09:30:23 PM PDT 24	19685912914 ps
T368	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2738556408			Jun 10 08:48:09 PM PDT 24	Jun 10 08:58:40 PM PDT 24	5434444752 ps
T736	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142998623			Jun 10 08:50:14 PM PDT 24	Jun 10 08:56:08 PM PDT 24	3522562388 ps
T244	/workspace/coverage/default/32.chip_sw_all_escalation_resets.3699921265			Jun 10 08:47:36 PM PDT 24	Jun 10 08:57:41 PM PDT 24	5259250900 ps
T151	/workspace/coverage/default/1.chip_sw_power_idle_load.2251031249			Jun 10 08:31:20 PM PDT 24	Jun 10 08:44:50 PM PDT 24	4254627834 ps
T215	/workspace/coverage/default/2.chip_sw_uart_tx_rx.2984424389			Jun 10 08:32:44 PM PDT 24	Jun 10 08:45:46 PM PDT 24	4082426664 ps
T369	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3352225681			Jun 10 08:48:06 PM PDT 24	Jun 10 08:56:18 PM PDT 24	6076402824 ps
T943	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1239848770			Jun 10 08:19:39 PM PDT 24	Jun 10 09:45:57 PM PDT 24	26507249780 ps
T83	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.328482176			Jun 10 08:27:19 PM PDT 24	Jun 10 08:31:37 PM PDT 24	3456839534 ps
T132	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4075238801			Jun 10 08:37:57 PM PDT 24	Jun 10 08:45:01 PM PDT 24	4824610468 ps
T944	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2861060765			Jun 10 08:23:06 PM PDT 24	Jun 10 08:31:12 PM PDT 24	4388943112 ps
T370	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2056515730			Jun 10 08:48:24 PM PDT 24	Jun 10 08:58:11 PM PDT 24	5387505134 ps
T60	/workspace/coverage/default/1.chip_sw_alert_test.3278475896			Jun 10 08:26:53 PM PDT 24	Jun 10 08:33:41 PM PDT 24	3497618732 ps
T28	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3686512059			Jun 10 08:32:44 PM PDT 24	Jun 10 08:48:46 PM PDT 24	8309215314 ps
T354	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.502605231			Jun 10 08:41:37 PM PDT 24	Jun 10 08:47:10 PM PDT 24	3257270516 ps
T182	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1072323612			Jun 10 08:22:57 PM PDT 24	Jun 10 08:26:27 PM PDT 24	2478586159 ps
T465	/workspace/coverage/default/2.chip_sw_kmac_entropy.4289290652			Jun 10 08:33:01 PM PDT 24	Jun 10 08:38:17 PM PDT 24	2798386214 ps
T945	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1923289644			Jun 10 08:45:26 PM PDT 24	Jun 10 09:33:12 PM PDT 24	10458758501 ps
T396	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2558045246			Jun 10 08:34:55 PM PDT 24	Jun 10 08:39:08 PM PDT 24	3326199784 ps
T114	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1986828804			Jun 10 08:25:51 PM PDT 24	Jun 10 09:22:55 PM PDT 24	18796333951 ps
T342	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1063454272			Jun 10 08:16:52 PM PDT 24	Jun 10 08:26:20 PM PDT 24	4140466296 ps
T222	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2443130038			Jun 10 08:18:49 PM PDT 24	Jun 10 08:39:16 PM PDT 24	7678331540 ps
T559	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.754544432			Jun 10 08:27:27 PM PDT 24	Jun 10 08:36:33 PM PDT 24	6546673384 ps
T946	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.4082324078			Jun 10 08:30:14 PM PDT 24	Jun 10 08:34:44 PM PDT 24	2879639692 ps
T109	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2609215339			Jun 10 08:19:40 PM PDT 24	Jun 10 08:30:22 PM PDT 24	19658789660 ps
T61	/workspace/coverage/default/2.chip_sw_alert_test.1193908937			Jun 10 08:37:09 PM PDT 24	Jun 10 08:43:01 PM PDT 24	3070001162 ps
T164	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3441440223			Jun 10 08:18:49 PM PDT 24	Jun 10 08:20:56 PM PDT 24	2592684070 ps
T247	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3838843998			Jun 10 08:27:56 PM PDT 24	Jun 10 08:46:24 PM PDT 24	8127279120 ps
T119	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.4056545858			Jun 10 08:34:13 PM PDT 24	Jun 10 10:02:23 PM PDT 24	47716862057 ps
T947	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1770000690			Jun 10 08:20:14 PM PDT 24	Jun 10 08:28:00 PM PDT 24	5107097384 ps
T32	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3575804992			Jun 10 08:25:52 PM PDT 24	Jun 10 09:16:59 PM PDT 24	21029728540 ps
T340	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3019848061			Jun 10 08:18:35 PM PDT 24	Jun 10 08:50:43 PM PDT 24	13027385043 ps
T948	/workspace/coverage/default/1.chip_sw_example_rom.2238781424			Jun 10 08:19:57 PM PDT 24	Jun 10 08:21:54 PM PDT 24	1926466440 ps
T223	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2056432641			Jun 10 08:34:41 PM PDT 24	Jun 10 08:57:32 PM PDT 24	9007131044 ps
T949	/workspace/coverage/default/2.chip_sw_otbn_randomness.2884796697			Jun 10 08:36:25 PM PDT 24	Jun 10 08:51:55 PM PDT 24	5618691960 ps
T855	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3391711979			Jun 10 08:49:21 PM PDT 24	Jun 10 09:00:00 PM PDT 24	5184851008 ps
T378	/workspace/coverage/default/21.chip_sw_all_escalation_resets.733458346			Jun 10 08:48:46 PM PDT 24	Jun 10 09:00:36 PM PDT 24	6298411216 ps
T950	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1064642045			Jun 10 08:20:29 PM PDT 24	Jun 10 08:28:06 PM PDT 24	5182891699 ps
T84	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896645486			Jun 10 08:51:37 PM PDT 24	Jun 10 08:58:39 PM PDT 24	3962731222 ps
T78	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3906036014			Jun 10 08:39:59 PM PDT 24	Jun 10 08:47:27 PM PDT 24	3771612360 ps
T210	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2753561459			Jun 10 08:23:46 PM PDT 24	Jun 11 12:01:52 AM PDT 24	79036362075 ps
T355	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.139808564			Jun 10 08:44:42 PM PDT 24	Jun 10 09:26:22 PM PDT 24	13257164024 ps
T951	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1605322883			Jun 10 08:27:27 PM PDT 24	Jun 10 08:30:45 PM PDT 24	2543631142 ps
T952	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1664446757			Jun 10 08:35:44 PM PDT 24	Jun 10 08:42:54 PM PDT 24	6685801394 ps
T953	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2245364403			Jun 10 08:47:01 PM PDT 24	Jun 10 08:54:54 PM PDT 24	3850046290 ps
T794	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1554964908			Jun 10 08:46:39 PM PDT 24	Jun 10 08:53:50 PM PDT 24	3226276530 ps
T265	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1535733921			Jun 10 08:43:44 PM PDT 24	Jun 10 08:52:44 PM PDT 24	4982967092 ps
T843	/workspace/coverage/default/86.chip_sw_all_escalation_resets.2974574948			Jun 10 08:50:19 PM PDT 24	Jun 10 09:01:08 PM PDT 24	5715754808 ps
T183	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2720397912			Jun 10 08:40:10 PM PDT 24	Jun 10 08:45:13 PM PDT 24	2917689458 ps
T184	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2183287903			Jun 10 08:23:30 PM PDT 24	Jun 10 08:39:41 PM PDT 24	9199660253 ps
T954	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2340176993			Jun 10 08:21:13 PM PDT 24	Jun 10 08:27:59 PM PDT 24	3065985528 ps
T251	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092824400			Jun 10 08:49:01 PM PDT 24	Jun 10 08:56:38 PM PDT 24	4390101342 ps
T187	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3221761999			Jun 10 08:38:00 PM PDT 24	Jun 10 08:46:42 PM PDT 24	3439346336 ps
T257	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3453281116			Jun 10 08:21:03 PM PDT 24	Jun 10 08:34:20 PM PDT 24	7142446824 ps
T258	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1021974446			Jun 10 08:18:39 PM PDT 24	Jun 10 08:30:33 PM PDT 24	4149535880 ps
T259	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1110706843			Jun 10 08:48:30 PM PDT 24	Jun 10 09:00:29 PM PDT 24	4929486896 ps
T260	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1532195172			Jun 10 08:29:56 PM PDT 24	Jun 10 08:34:19 PM PDT 24	2474447140 ps
T261	/workspace/coverage/default/2.chip_sw_example_flash.114358452			Jun 10 08:33:27 PM PDT 24	Jun 10 08:38:51 PM PDT 24	3076664640 ps
T216	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2794125146			Jun 10 08:25:17 PM PDT 24	Jun 10 08:51:31 PM PDT 24	8284039016 ps
T262	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.407508781			Jun 10 08:24:23 PM PDT 24	Jun 10 08:35:11 PM PDT 24	4182923676 ps
T263	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.557261316			Jun 10 08:52:01 PM PDT 24	Jun 10 08:59:06 PM PDT 24	3277098862 ps
T161	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3597700260			Jun 10 08:33:32 PM PDT 24	Jun 10 08:38:12 PM PDT 24	3014226549 ps
T123	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3073233638			Jun 10 08:18:32 PM PDT 24	Jun 10 08:29:16 PM PDT 24	4132231902 ps
T955	/workspace/coverage/default/2.chip_sw_example_concurrency.2048253421			Jun 10 08:32:56 PM PDT 24	Jun 10 08:37:13 PM PDT 24	2878454242 ps
T225	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1439554009			Jun 10 08:29:09 PM PDT 24	Jun 10 09:14:27 PM PDT 24	11335399220 ps
T956	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2018180187			Jun 10 08:20:04 PM PDT 24	Jun 10 08:30:17 PM PDT 24	5190287254 ps
T957	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1955440292			Jun 10 08:37:09 PM PDT 24	Jun 10 09:44:57 PM PDT 24	41245656990 ps
T776	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551872948			Jun 10 08:48:21 PM PDT 24	Jun 10 08:53:58 PM PDT 24	3562992200 ps
T958	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.26955177			Jun 10 08:27:41 PM PDT 24	Jun 10 09:23:53 PM PDT 24	15001361830 ps
T120	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.983887428			Jun 10 08:44:01 PM PDT 24	Jun 10 08:59:10 PM PDT 24	10687162529 ps
T170	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3397886640			Jun 10 08:28:12 PM PDT 24	Jun 10 09:35:34 PM PDT 24	14730604500 ps
T959	/workspace/coverage/default/2.chip_sw_example_rom.2839624101			Jun 10 08:31:11 PM PDT 24	Jun 10 08:33:44 PM PDT 24	2629269728 ps
T960	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1794283828			Jun 10 08:44:13 PM PDT 24	Jun 10 09:18:53 PM PDT 24	12856808088 ps
T110	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3521905184			Jun 10 08:30:16 PM PDT 24	Jun 10 09:17:57 PM PDT 24	20034498424 ps
T832	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1069347971			Jun 10 08:46:59 PM PDT 24	Jun 10 08:53:43 PM PDT 24	3618457672 ps
T760	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.695365660			Jun 10 08:47:45 PM PDT 24	Jun 10 08:53:30 PM PDT 24	4165085864 ps
T303	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.820820562			Jun 10 08:26:39 PM PDT 24	Jun 10 08:35:17 PM PDT 24	4447931370 ps
T961	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.521167020			Jun 10 08:24:47 PM PDT 24	Jun 10 08:37:54 PM PDT 24	6859714704 ps
T252	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2405549360			Jun 10 08:45:42 PM PDT 24	Jun 10 08:55:53 PM PDT 24	4663901668 ps
T962	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3009388379			Jun 10 08:41:31 PM PDT 24	Jun 10 08:46:45 PM PDT 24	2640756840 ps
T963	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1856985424			Jun 10 08:20:34 PM PDT 24	Jun 10 08:27:39 PM PDT 24	7162255332 ps
T964	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1396195791			Jun 10 08:28:51 PM PDT 24	Jun 10 08:38:11 PM PDT 24	5056230128 ps
T797	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392380881			Jun 10 08:50:25 PM PDT 24	Jun 10 08:56:05 PM PDT 24	3751861270 ps
T965	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1732157340			Jun 10 08:27:27 PM PDT 24	Jun 10 08:31:48 PM PDT 24	2936098280 ps
T966	/workspace/coverage/default/0.rom_e2e_asm_init_rma.627278540			Jun 10 08:27:31 PM PDT 24	Jun 10 09:29:58 PM PDT 24	14348480093 ps
T967	/workspace/coverage/default/2.chip_sw_hmac_multistream.1912721131			Jun 10 08:38:08 PM PDT 24	Jun 10 09:02:26 PM PDT 24	6410422736 ps
T828	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3836708736			Jun 10 08:47:49 PM PDT 24	Jun 10 08:59:04 PM PDT 24	6316630938 ps
T346	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.665614841			Jun 10 08:25:18 PM PDT 24	Jun 10 08:41:26 PM PDT 24	4623102744 ps
T850	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3395061586			Jun 10 08:46:23 PM PDT 24	Jun 10 08:52:05 PM PDT 24	3567054340 ps
T171	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2808714973			Jun 10 08:34:16 PM PDT 24	Jun 10 10:15:31 PM PDT 24	51147568280 ps
T968	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1751844179			Jun 10 08:41:05 PM PDT 24	Jun 10 08:44:50 PM PDT 24	2782346664 ps
T969	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.189715647			Jun 10 08:23:33 PM PDT 24	Jun 10 08:27:40 PM PDT 24	2761830552 ps
T365	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2111553095			Jun 10 08:33:50 PM PDT 24	Jun 10 08:48:09 PM PDT 24	4662167412 ps
T970	/workspace/coverage/default/1.chip_sw_kmac_idle.1548019272			Jun 10 08:28:21 PM PDT 24	Jun 10 08:33:23 PM PDT 24	2516606490 ps
T971	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3886725101			Jun 10 08:26:08 PM PDT 24	Jun 10 08:59:03 PM PDT 24	9119507820 ps
T972	/workspace/coverage/default/0.rom_e2e_static_critical.2870959851			Jun 10 08:28:24 PM PDT 24	Jun 10 09:42:22 PM PDT 24	16609159560 ps
T227	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2327863984			Jun 10 08:30:19 PM PDT 24	Jun 10 08:45:28 PM PDT 24	6494337840 ps
T160	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3336144115			Jun 10 08:37:17 PM PDT 24	Jun 10 11:37:06 PM PDT 24	256237965710 ps
T146	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.981599117			Jun 10 08:17:56 PM PDT 24	Jun 10 08:24:05 PM PDT 24	7816917500 ps
T226	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.190576171			Jun 10 08:27:18 PM PDT 24	Jun 10 08:57:47 PM PDT 24	8132978156 ps
T273	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4061818194			Jun 10 08:30:57 PM PDT 24	Jun 10 08:35:58 PM PDT 24	2490921592 ps
T762	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.910601914			Jun 10 08:44:24 PM PDT 24	Jun 10 08:52:00 PM PDT 24	4213645690 ps
T973	/workspace/coverage/default/0.rom_keymgr_functest.2231075536			Jun 10 08:24:01 PM PDT 24	Jun 10 08:31:59 PM PDT 24	4064401684 ps
T345	/workspace/coverage/default/2.chip_plic_all_irqs_0.3798893917			Jun 10 08:38:33 PM PDT 24	Jun 10 08:59:29 PM PDT 24	6739684038 ps
T974	/workspace/coverage/default/1.rom_e2e_static_critical.2090801338			Jun 10 08:37:12 PM PDT 24	Jun 10 09:35:13 PM PDT 24	16520122880 ps
T975	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3545884763			Jun 10 08:35:24 PM PDT 24	Jun 10 08:56:27 PM PDT 24	13040124385 ps
T229	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3332782356			Jun 10 08:23:05 PM PDT 24	Jun 10 08:39:43 PM PDT 24	6671721767 ps
T403	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.886191631			Jun 10 08:28:12 PM PDT 24	Jun 10 10:03:16 PM PDT 24	17891937868 ps
T844	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.181132449			Jun 10 08:47:06 PM PDT 24	Jun 10 08:56:01 PM PDT 24	4395765268 ps
T976	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2386050604			Jun 10 08:23:47 PM PDT 24	Jun 10 08:44:49 PM PDT 24	5569891532 ps
T763	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1133559703			Jun 10 08:48:12 PM PDT 24	Jun 10 08:54:15 PM PDT 24	3268839990 ps
T236	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2946412850			Jun 10 08:39:09 PM PDT 24	Jun 10 09:10:56 PM PDT 24	22842827621 ps
T977	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1562021392			Jun 10 08:18:50 PM PDT 24	Jun 10 08:43:07 PM PDT 24	9396880872 ps
T266	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1060728746			Jun 10 08:34:39 PM PDT 24	Jun 10 08:47:04 PM PDT 24	7103274120 ps
T279	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2239589389			Jun 10 08:43:58 PM PDT 24	Jun 10 09:26:04 PM PDT 24	11514857664 ps
T282	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020554445			Jun 10 08:50:03 PM PDT 24	Jun 10 08:57:00 PM PDT 24	3573047080 ps