Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141735	1			T75	18		T76	44		T77	58
values[2]	10934	1			T77	3		T271	1		T469	233
values[3]	4889	1			T271	1		T469	139		T563	7
values[4]	3067	1			T271	1		T469	105		T563	1
values[5]	1821	1			T271	1		T469	56		T445	6
values[6]	1263	1			T271	1		T469	57		T445	6
values[7]	975	1			T271	1		T469	43		T445	5
values[8]	847	1			T271	1		T469	20		T445	12
values[9]	675	1			T271	1		T469	3		T445	11
values[10]	558	1			T271	1		T445	7		T452	2
values[11]	553	1			T271	1		T445	11		T452	2
values[12]	500	1			T271	1		T445	6		T452	2
values[13]	481	1			T271	1		T445	13		T452	2
values[14]	488	1			T271	1		T445	6		T452	2
values[15]	400	1			T271	1		T445	3		T452	2
values[16]	429	1			T271	1		T445	9		T452	2
values[17]	349	1			T271	1		T445	6		T452	2
values[18]	405	1			T271	1		T445	6		T452	2
values[19]	426	1			T271	1		T445	5		T452	2
values[20]	408	1			T271	1		T445	3		T452	2
values[21]	399	1			T271	1		T445	3		T452	2
values[22]	365	1			T271	1		T445	3		T452	2
values[23]	370	1			T271	1		T445	25		T452	2
values[24]	437	1			T271	1		T445	7		T452	2
values[25]	398	1			T271	1		T445	5		T452	2
values[26]	397	1			T271	1		T445	6		T452	2
values[27]	384	1			T271	1		T445	4		T452	2
values[28]	385	1			T271	1		T445	5		T452	2
values[29]	313	1			T271	1		T445	4		T452	2
values[30]	336	1			T271	1		T445	4		T452	2
values[31]	339	1			T271	1		T445	6		T452	2
values[32]	336	1			T271	1		T445	3		T452	2
values[33]	318	1			T271	1		T445	4		T452	2
values[34]	372	1			T271	1		T445	4		T452	2
values[35]	343	1			T271	1		T445	3		T452	2
values[36]	367	1			T271	1		T445	4		T452	2
values[37]	396	1			T271	1		T445	29		T452	2
values[38]	376	1			T271	1		T445	16		T452	2
values[39]	358	1			T271	1		T445	4		T452	2
values[40]	325	1			T271	1		T445	6		T452	2
values[41]	394	1			T271	1		T445	7		T452	2
values[42]	348	1			T271	1		T445	3		T452	2
values[43]	332	1			T271	1		T445	7		T452	2
values[44]	341	1			T271	1		T445	9		T452	2
values[45]	328	1			T271	1		T445	5		T452	2
values[46]	366	1			T271	1		T445	5		T452	2
values[47]	355	1			T271	1		T445	12		T452	2
values[48]	269	1			T271	1		T445	15		T452	2
values[49]	274	1			T271	1		T445	4		T452	2
values[50]	291	1			T271	1		T445	3		T452	2
values[51]	307	1			T271	1		T445	10		T452	2
values[52]	283	1			T271	1		T445	5		T452	2
values[53]	274	1			T271	1		T445	6		T452	2
values[54]	278	1			T271	1		T445	3		T452	2
values[55]	300	1			T271	1		T445	4		T452	2
values[56]	254	1			T271	1		T445	3		T452	2
values[57]	256	1			T271	1		T445	6		T452	2
values[58]	238	1			T271	1		T445	14		T452	2
values[59]	232	1			T271	1		T445	13		T452	2
values[60]	217	1			T271	3		T445	6		T452	2
values[61]	218	1			T271	1		T445	14		T452	2
values[62]	225	1			T271	1		T445	17		T452	2
values[63]	181	1			T271	1		T445	3		T452	2
values[64]	193	1			T271	1		T452	2		T499	1
values[65]	153	1			T271	1		T452	2		T499	1
values[66]	158	1			T271	1		T452	2		T499	1
values[67]	174	1			T271	1		T452	2		T499	1
values[68]	171	1			T271	1		T452	2		T499	1
values[69]	200	1			T271	1		T452	2		T499	1
values[70]	186	1			T271	1		T452	2		T499	1
values[71]	139	1			T271	1		T452	2		T499	1
values[72]	168	1			T271	1		T452	2		T499	1
values[73]	133	1			T271	1		T452	2		T499	1
values[74]	141	1			T271	1		T452	2		T499	1
values[75]	124	1			T271	1		T452	2		T499	1
values[76]	139	1			T271	1		T452	2		T499	1
values[77]	122	1			T271	1		T452	2		T499	1
values[78]	106	1			T271	1		T452	2		T499	1
values[79]	109	1			T271	1		T452	2		T499	1
values[80]	138	1			T271	1		T452	2		T499	1
values[81]	116	1			T271	1		T452	2		T499	1
values[82]	103	1			T271	1		T452	2		T499	1
values[83]	103	1			T271	2		T452	2		T499	1
values[84]	87	1			T271	1		T452	2		T499	1
values[85]	108	1			T271	1		T452	2		T499	1
values[86]	77	1			T271	1		T452	2		T499	1
values[87]	87	1			T271	1		T452	2		T499	1
values[88]	82	1			T271	1		T452	2		T499	1
values[89]	105	1			T271	1		T452	2		T499	1
values[90]	115	1			T271	1		T452	2		T499	1
values[91]	80	1			T271	1		T452	2		T499	1
values[92]	94	1			T271	1		T452	2		T499	1
values[93]	101	1			T271	1		T452	2		T499	1
values[94]	96	1			T271	1		T452	2		T499	1
values[95]	94	1			T271	1		T452	2		T499	1
values[96]	82	1			T271	1		T452	2		T499	1
values[97]	66	1			T271	1		T452	2		T499	1
values[98]	83	1			T271	1		T452	2		T499	1
values[99]	82	1			T271	1		T452	2		T499	1
values[100]	100	1			T271	2		T452	4		T499	2
values[101]	93	1			T271	5		T452	2		T499	1
values[102]	89	1			T271	4		T452	2		T499	1
values[103]	107	1			T271	1		T452	2		T499	1
values[104]	119	1			T271	4		T452	2		T499	1
values[105]	97	1			T271	4		T452	2		T499	1
values[106]	90	1			T271	3		T452	2		T499	1
values[107]	87	1			T271	4		T452	2		T499	1
values[108]	96	1			T271	2		T452	2		T499	1
values[109]	75	1			T271	1		T452	4		T499	1
values[110]	95	1			T271	3		T452	2		T499	1
values[111]	69	1			T271	4		T452	3		T499	1
values[112]	87	1			T271	2		T452	3		T499	6
values[113]	89	1			T271	4		T452	2		T499	1
values[114]	74	1			T271	1		T452	6		T499	1
values[115]	70	1			T271	2		T452	3		T499	1
values[116]	71	1			T271	3		T452	6		T499	1
values[117]	67	1			T271	1		T452	5		T499	7
values[118]	76	1			T271	2		T452	2		T499	1
values[119]	80	1			T271	1		T452	2		T499	3
values[120]	74	1			T271	1		T452	7		T499	2
values[121]	63	1			T271	1		T452	3		T499	1
values[122]	57	1			T271	4		T452	4		T499	1
values[123]	56	1			T271	1		T452	3		T499	4
values[124]	39	1			T271	1		T452	4		T499	1
values[125]	53	1			T271	2		T452	2		T499	1
values[126]	89	1			T271	2		T452	5		T499	9
values[127]	612	1			T271	27		T452	45		T499	30
values[128]	5825	1			T271	290		T452	621		T499	278