Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	485	1			T271	1		T557	2		T561	1
all_values[1]	457	1			T560	3		T563	1		T716	1
all_values[2]	458	1			T557	3		T560	2		T563	3
all_values[3]	418	1			T469	2		T557	3		T564	1
all_values[4]	447	1			T271	1		T557	2		T564	1
all_values[5]	442	1			T557	2		T561	1		T560	3
all_values[6]	415	1			T557	1		T561	1		T560	2
all_values[7]	436	1			T469	1		T557	2		T564	1
all_values[8]	446	1			T557	5		T564	1		T561	2
all_values[9]	449	1			T557	2		T568	1		T876	4
all_values[10]	456	1			T271	1		T469	1		T557	3
all_values[11]	438	1			T557	2		T560	1		T563	2
all_values[12]	454	1			T469	2		T557	3		T865	1
all_values[13]	450	1			T557	2		T568	2		T560	2
all_values[14]	455	1			T557	5		T560	2		T563	3
all_values[15]	447	1			T557	2		T564	1		T561	2
all_values[16]	418	1			T469	2		T557	1		T564	1
all_values[17]	469	1			T557	6		T568	1		T560	2
all_values[18]	427	1			T557	5		T561	1		T560	1
all_values[19]	422	1			T469	1		T557	1		T561	2
all_values[20]	485	1			T469	1		T564	1		T561	1
all_values[21]	459	1			T557	1		T561	1		T568	1
all_values[22]	443	1			T557	2		T561	2		T560	3
all_values[23]	468	1			T271	1		T557	4		T561	1
all_values[24]	431	1			T557	2		T564	1		T561	1
all_values[25]	511	1			T557	1		T561	2		T560	2
all_values[26]	447	1			T271	1		T773	1		T557	2
all_values[27]	463	1			T557	4		T561	1		T560	2
all_values[28]	452	1			T557	1		T564	1		T561	2
all_values[29]	438	1			T557	4		T561	1		T560	1
all_values[30]	446	1			T557	1		T564	1		T561	2
all_values[31]	485	1			T557	3		T564	2		T561	2
all_values[32]	443	1			T469	1		T557	1		T560	4
all_values[33]	428	1			T271	1		T557	2		T564	1
all_values[34]	435	1			T271	1		T469	1		T557	2
all_values[35]	444	1			T271	1		T469	3		T557	2
all_values[36]	444	1			T557	9		T560	1		T563	2
all_values[37]	423	1			T564	1		T561	1		T560	3
all_values[38]	449	1			T557	2		T568	1		T563	1
all_values[39]	480	1			T271	1		T557	3		T568	1
all_values[40]	426	1			T557	1		T561	1		T563	1
all_values[41]	466	1			T469	1		T557	2		T564	1
all_values[42]	474	1			T469	2		T557	5		T564	2
all_values[43]	429	1			T557	5		T560	2		T563	1
all_values[44]	457	1			T271	1		T469	2		T564	1
all_values[45]	432	1			T557	1		T564	2		T561	2
all_values[46]	467	1			T564	2		T560	4		T865	2
all_values[47]	469	1			T271	1		T557	3		T561	1
all_values[48]	457	1			T271	1		T557	5		T560	1
all_values[49]	453	1			T557	2		T564	4		T568	1