Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3387	1			T208	1		T557	11		T558	6
all_values[1]	3428	1			T75	1		T208	1		T469	1
all_values[2]	3379	1			T75	1		T208	1		T469	1
all_values[3]	3478	1			T75	2		T557	21		T558	1
all_values[4]	3422	1			T208	1		T469	1		T557	14
all_values[5]	3546	1			T75	1		T469	2		T557	12
all_values[6]	3502	1			T469	1		T557	13		T558	1
all_values[7]	3313	1			T208	4		T557	16		T564	3
all_values[8]	3395	1			T75	1		T469	1		T557	18
all_values[9]	3378	1			T557	12		T558	1		T564	2
all_values[10]	3331	1			T75	1		T208	1		T557	18
all_values[11]	3343	1			T75	1		T208	2		T557	12
all_values[12]	3253	1			T208	1		T469	1		T557	17
all_values[13]	3394	1			T557	21		T558	1		T564	3
all_values[14]	3521	1			T208	1		T469	2		T557	12
all_values[15]	3481	1			T557	17		T558	1		T564	7
all_values[16]	3408	1			T75	1		T208	3		T469	2
all_values[17]	3381	1			T557	16		T558	1		T564	3
all_values[18]	3412	1			T208	3		T469	1		T557	13
all_values[19]	3434	1			T75	1		T208	1		T469	1
all_values[20]	3377	1			T208	1		T469	3		T557	17
all_values[21]	3445	1			T75	1		T208	3		T557	20
all_values[22]	3374	1			T469	1		T557	21		T558	1
all_values[23]	3449	1			T208	1		T557	19		T558	3
all_values[24]	3362	1			T557	17		T558	2		T564	4
all_values[25]	3384	1			T75	1		T557	13		T558	2
all_values[26]	3267	1			T75	1		T208	2		T557	17
all_values[27]	3356	1			T208	1		T469	2		T557	18
all_values[28]	3490	1			T75	1		T208	4		T557	21
all_values[29]	3322	1			T469	2		T557	17		T558	3
all_values[30]	3430	1			T75	2		T208	3		T469	1
all_values[31]	3514	1			T208	1		T469	2		T557	23
all_values[32]	3413	1			T208	2		T469	1		T557	17
all_values[33]	3457	1			T75	1		T208	2		T469	1
all_values[34]	3349	1			T208	3		T557	17		T558	2
all_values[35]	3489	1			T75	1		T208	1		T557	8
all_values[36]	3412	1			T208	2		T557	16		T558	1
all_values[37]	3459	1			T557	19		T558	1		T564	2
all_values[38]	3493	1			T469	1		T557	19		T564	4
all_values[39]	3357	1			T75	1		T208	1		T557	14
all_values[40]	3411	1			T208	2		T469	1		T557	16
all_values[41]	3375	1			T208	1		T469	1		T557	17
all_values[42]	3508	1			T208	1		T469	1		T557	16
all_values[43]	3455	1			T75	1		T208	1		T557	16
all_values[44]	3409	1			T557	19		T558	4		T564	4
all_values[45]	3455	1			T208	1		T469	2		T557	24
all_values[46]	3433	1			T75	1		T208	1		T469	1
all_values[47]	3324	1			T469	1		T557	15		T564	4
all_values[48]	3419	1			T208	2		T469	1		T557	18
all_values[49]	3360	1			T469	1		T557	9		T564	3
all_values[50]	3330	1			T75	1		T557	16		T558	2
all_values[51]	3397	1			T557	18		T558	1		T564	5
all_values[52]	3387	1			T75	1		T208	1		T469	1
all_values[53]	3411	1			T75	1		T557	22		T558	2
all_values[54]	3390	1			T208	3		T557	25		T558	1
all_values[55]	3344	1			T469	1		T557	15		T558	2
all_values[56]	3422	1			T75	1		T469	1		T557	22
all_values[57]	3427	1			T75	2		T208	1		T557	20
all_values[58]	3410	1			T75	1		T208	1		T557	11
all_values[59]	3496	1			T208	1		T469	2		T557	12
all_values[60]	3438	1			T75	1		T208	1		T469	2
all_values[61]	3349	1			T208	1		T557	17		T558	1
all_values[62]	3445	1			T75	1		T557	12		T558	4
all_values[63]	3304	1			T75	2		T557	17		T564	3