Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135353	1			T75	66		T76	1		T77	7
values[2]	10445	1			T75	1		T76	1		T79	9
values[3]	4508	1			T76	1		T480	1		T513	1
values[4]	2618	1			T76	1		T785	58		T490	6
values[5]	1751	1			T76	1		T785	41		T490	2
values[6]	1185	1			T76	1		T785	22		T429	6
values[7]	800	1			T76	1		T785	12		T429	1
values[8]	625	1			T76	1		T785	12		T430	1
values[9]	599	1			T76	1		T785	6		T430	1
values[10]	484	1			T76	1		T430	1		T792	1
values[11]	371	1			T76	1		T430	1		T792	1
values[12]	337	1			T76	1		T430	1		T792	1
values[13]	323	1			T76	1		T430	1		T792	1
values[14]	325	1			T76	1		T430	1		T792	1
values[15]	302	1			T76	1		T430	1		T792	1
values[16]	315	1			T76	1		T430	1		T792	1
values[17]	255	1			T76	1		T430	1		T792	1
values[18]	318	1			T76	1		T430	1		T792	1
values[19]	285	1			T76	1		T430	1		T792	1
values[20]	322	1			T76	1		T430	1		T792	1
values[21]	283	1			T76	1		T430	1		T792	1
values[22]	252	1			T76	1		T430	1		T792	1
values[23]	230	1			T76	1		T430	1		T792	1
values[24]	270	1			T76	1		T430	1		T792	1
values[25]	257	1			T76	1		T430	1		T792	1
values[26]	303	1			T76	1		T430	1		T792	1
values[27]	307	1			T76	1		T430	1		T792	1
values[28]	270	1			T76	1		T430	1		T792	1
values[29]	269	1			T76	1		T430	1		T792	1
values[30]	257	1			T76	1		T430	1		T792	1
values[31]	291	1			T76	1		T430	1		T792	1
values[32]	242	1			T76	1		T430	1		T792	1
values[33]	232	1			T76	1		T430	1		T792	1
values[34]	281	1			T76	1		T430	1		T792	1
values[35]	307	1			T76	1		T430	1		T792	1
values[36]	268	1			T76	1		T430	1		T792	1
values[37]	245	1			T76	1		T430	1		T792	1
values[38]	240	1			T76	1		T430	1		T792	1
values[39]	231	1			T76	1		T430	1		T792	1
values[40]	275	1			T76	1		T430	1		T792	1
values[41]	285	1			T76	1		T430	1		T792	1
values[42]	238	1			T76	1		T430	1		T792	1
values[43]	247	1			T76	1		T430	1		T792	1
values[44]	223	1			T76	1		T430	1		T792	1
values[45]	244	1			T76	1		T430	1		T792	1
values[46]	248	1			T76	1		T430	1		T792	1
values[47]	258	1			T76	1		T430	1		T792	1
values[48]	220	1			T76	1		T430	1		T792	1
values[49]	209	1			T76	1		T430	1		T792	1
values[50]	206	1			T76	1		T430	1		T792	1
values[51]	226	1			T76	1		T430	1		T792	1
values[52]	212	1			T76	1		T430	1		T792	1
values[53]	207	1			T76	1		T430	1		T792	1
values[54]	271	1			T76	1		T430	1		T792	1
values[55]	212	1			T76	1		T430	1		T792	1
values[56]	174	1			T76	1		T430	1		T792	1
values[57]	224	1			T76	1		T430	1		T792	1
values[58]	196	1			T76	1		T430	1		T792	1
values[59]	230	1			T76	1		T430	1		T792	1
values[60]	206	1			T76	1		T430	1		T792	1
values[61]	199	1			T76	1		T430	1		T792	1
values[62]	189	1			T76	1		T430	1		T792	1
values[63]	168	1			T76	1		T430	1		T792	1
values[64]	143	1			T76	1		T430	1		T792	1
values[65]	183	1			T76	1		T430	1		T792	1
values[66]	123	1			T76	1		T430	1		T792	1
values[67]	148	1			T76	1		T430	1		T792	1
values[68]	110	1			T76	1		T430	1		T792	1
values[69]	119	1			T76	1		T430	1		T792	1
values[70]	100	1			T76	1		T430	1		T792	1
values[71]	91	1			T76	1		T430	1		T792	1
values[72]	76	1			T76	1		T430	1		T792	1
values[73]	73	1			T76	1		T430	1		T792	1
values[74]	76	1			T76	1		T430	1		T792	1
values[75]	77	1			T76	1		T430	1		T792	1
values[76]	71	1			T76	1		T430	1		T792	1
values[77]	80	1			T76	1		T430	1		T792	1
values[78]	68	1			T76	1		T430	1		T792	1
values[79]	64	1			T76	1		T430	2		T792	1
values[80]	65	1			T76	1		T430	1		T792	1
values[81]	82	1			T76	1		T430	1		T792	1
values[82]	72	1			T76	1		T430	1		T792	1
values[83]	84	1			T76	1		T430	1		T792	1
values[84]	86	1			T76	1		T430	1		T792	1
values[85]	77	1			T76	1		T430	1		T792	1
values[86]	70	1			T76	1		T430	1		T792	1
values[87]	75	1			T76	1		T430	1		T792	1
values[88]	87	1			T76	1		T430	1		T792	1
values[89]	78	1			T76	1		T430	1		T792	1
values[90]	95	1			T76	1		T430	1		T792	1
values[91]	84	1			T76	1		T430	1		T792	1
values[92]	89	1			T76	3		T430	2		T792	1
values[93]	83	1			T76	4		T430	1		T792	1
values[94]	87	1			T76	5		T430	2		T792	1
values[95]	82	1			T76	1		T430	6		T792	1
values[96]	83	1			T76	1		T430	2		T792	1
values[97]	74	1			T76	4		T430	2		T792	1
values[98]	79	1			T76	3		T430	3		T792	1
values[99]	99	1			T76	3		T430	1		T792	2
values[100]	91	1			T76	4		T430	1		T792	1
values[101]	79	1			T76	4		T430	3		T792	1
values[102]	102	1			T76	9		T430	1		T792	1
values[103]	99	1			T76	1		T430	3		T792	1
values[104]	96	1			T76	1		T430	3		T792	1
values[105]	100	1			T76	1		T430	3		T792	1
values[106]	96	1			T76	1		T430	1		T792	1
values[107]	81	1			T76	3		T430	1		T792	1
values[108]	78	1			T76	2		T430	5		T792	1
values[109]	104	1			T76	3		T430	3		T792	1
values[110]	71	1			T76	4		T430	2		T792	1
values[111]	80	1			T76	2		T430	1		T792	1
values[112]	81	1			T76	2		T430	2		T792	1
values[113]	86	1			T76	1		T430	4		T792	1
values[114]	86	1			T76	1		T430	1		T792	1
values[115]	76	1			T76	3		T430	4		T792	1
values[116]	90	1			T76	1		T430	1		T792	1
values[117]	92	1			T76	1		T430	2		T792	1
values[118]	114	1			T76	1		T430	4		T792	1
values[119]	92	1			T76	1		T430	3		T792	3
values[120]	100	1			T76	3		T430	2		T792	1
values[121]	87	1			T76	2		T430	1		T792	2
values[122]	93	1			T76	2		T430	1		T792	2
values[123]	83	1			T76	1		T430	4		T792	2
values[124]	87	1			T76	1		T430	2		T792	1
values[125]	127	1			T76	1		T430	3		T792	2
values[126]	223	1			T76	2		T430	1		T792	4
values[127]	950	1			T76	37		T430	41		T792	30
values[128]	7172	1			T76	316		T430	334		T792	295