Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	95.52	93.75	95.49		94.47	97.53	99.64

Total tests in report: 2896

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.48	39.48	44.68	44.68	42.95	42.95	31.52	31.52			57.87	57.87	59.44	59.44	0.39	0.39	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1166641058
50.32	10.85	56.62	11.93	55.92	12.96	36.63	5.11			67.59	9.72	83.57	24.13	1.62	1.23	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.152958488
57.67	7.34	62.13	5.51	59.56	3.64	38.24	1.62			67.86	0.27	83.57	0.00	34.64	33.02	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3620429226
62.72	5.06	72.87	10.74	66.38	6.82	41.93	3.69			76.58	8.72	83.74	0.17	34.84	0.20	/workspace/coverage/default/2.chip_jtag_csr_rw.601481631
66.19	3.47	78.86	5.99	70.70	4.33	45.84	3.91			78.60	2.02	88.29	4.55	34.84	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1515976748
69.38	3.20	78.86	0.00	70.70	0.00	45.84	0.00			78.60	0.00	88.29	0.00	54.01	19.18	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.184209867
72.42	3.04	78.87	0.01	70.72	0.02	64.02	18.18			78.62	0.02	88.29	0.00	54.01	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4108100968
74.74	2.31	80.14	1.27	73.15	2.42	70.66	6.63			80.36	1.74	88.29	0.00	55.82	1.81	/workspace/coverage/default/2.chip_sw_alert_test.1327823568
76.99	2.26	80.14	0.00	73.59	0.44	70.66	0.00			80.36	0.00	88.29	0.00	68.91	13.09	/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3032947251
78.62	1.63	80.41	0.27	73.74	0.15	79.46	8.81			80.54	0.18	88.64	0.35	68.91	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2555362215
80.10	1.48	82.05	1.64	77.16	3.42	79.68	0.21			83.80	3.26	88.99	0.35	68.91	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1122985311
81.47	1.37	82.07	0.02	78.44	1.28	80.85	1.17			84.08	0.28	88.99	0.00	74.39	5.48	/workspace/coverage/cover_reg_top/6.xbar_stress_all.1098522659
82.78	1.31	84.50	2.42	80.51	2.07	81.78	0.93			86.51	2.43	88.99	0.00	74.39	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3221270196
84.00	1.22	84.50	0.00	80.51	0.00	81.78	0.00			86.51	0.00	88.99	0.00	81.73	7.34	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2463340362
84.98	0.98	85.58	1.08	81.22	0.71	83.46	1.68			87.35	0.84	90.56	1.57	81.73	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1630444635
85.95	0.97	85.58	0.00	81.30	0.08	83.46	0.00			87.35	0.00	90.56	0.00	87.48	5.75	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1618065782
86.78	0.83	86.29	0.72	81.47	0.17	83.50	0.04			87.54	0.19	94.41	3.85	87.48	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1393165749
87.59	0.81	87.68	1.38	82.31	0.85	85.40	1.91			88.10	0.56	94.58	0.17	87.48	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2385927138
88.35	0.76	88.99	1.31	83.43	1.11	86.29	0.88			89.36	1.27	94.58	0.00	87.48	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1708783917
89.01	0.66	89.67	0.68	84.91	1.48	86.31	0.02			90.08	0.71	95.63	1.05	87.48	0.00	/workspace/coverage/cover_reg_top/11.chip_csr_rw.2478114607
89.60	0.59	90.71	1.04	85.97	1.06	86.70	0.39			91.10	1.02	95.63	0.00	87.48	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1103950889
90.15	0.56	90.71	0.00	85.97	0.00	86.70	0.00			91.10	0.00	95.63	0.00	90.82	3.35	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3994182398
90.63	0.47	90.71	0.01	86.06	0.10	87.39	0.69			91.13	0.03	95.63	0.00	92.84	2.02	/workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3716067026
91.09	0.46	90.72	0.01	88.40	2.34	87.39	0.00			91.13	0.00	95.63	0.00	93.27	0.42	/workspace/coverage/cover_reg_top/15.chip_tl_errors.681881960
91.50	0.41	91.48	0.75	88.91	0.51	87.77	0.38			91.94	0.81	95.63	0.00	93.27	0.00	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3464728593
91.85	0.35	91.48	0.00	88.91	0.00	87.77	0.00			91.94	0.00	95.63	0.00	95.36	2.09	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2529307014
92.19	0.34	91.49	0.01	88.91	0.01	89.81	2.04			91.94	0.00	95.63	0.00	95.36	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1050619913
92.46	0.27	92.34	0.85	89.12	0.21	89.94	0.12			92.05	0.11	95.98	0.35	95.36	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2534751856
92.70	0.24	92.82	0.48	89.55	0.43	90.05	0.11			92.46	0.41	95.98	0.00	95.36	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2554443039
92.90	0.20	92.82	0.00	89.57	0.02	90.05	0.00			92.46	0.00	95.98	0.00	96.52	1.16	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2339789206
93.08	0.18	93.07	0.26	89.68	0.11	90.71	0.66			92.53	0.06	95.98	0.00	96.52	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1735593720
93.24	0.16	93.36	0.28	90.00	0.32	91.07	0.36			92.53	0.00	95.98	0.00	96.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3378026961
93.39	0.15	93.53	0.17	90.12	0.11	91.21	0.14			92.65	0.12	96.33	0.35	96.52	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2812645314
93.53	0.14	93.53	0.00	90.13	0.02	91.21	0.00			92.65	0.00	96.33	0.00	97.34	0.82	/workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1341388249
93.67	0.14	93.57	0.04	90.48	0.35	91.24	0.03			93.04	0.39	96.33	0.00	97.34	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.502540151
93.79	0.12	93.57	0.00	90.48	0.00	91.98	0.74			93.04	0.00	96.33	0.00	97.34	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.945103717
93.92	0.12	93.80	0.22	90.67	0.19	92.00	0.01			93.35	0.32	96.33	0.00	97.34	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1146684785
94.04	0.12	93.94	0.14	90.85	0.18	92.03	0.03			93.54	0.19	96.50	0.17	97.36	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1666256193
94.15	0.11	94.12	0.18	91.08	0.22	92.13	0.10			93.73	0.19	96.50	0.00	97.36	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2754699389
94.26	0.10	94.12	0.00	91.18	0.10	92.17	0.03			93.74	0.02	96.50	0.00	97.83	0.47	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1323880280
94.34	0.08	94.12	0.00	91.68	0.51	92.17	0.00			93.74	0.00	96.50	0.00	97.83	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.3930806275
94.42	0.08	94.12	0.00	91.68	0.00	92.64	0.47			93.74	0.00	96.50	0.00	97.83	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1463291943
94.49	0.08	94.12	0.00	91.68	0.00	93.09	0.45			93.74	0.00	96.50	0.00	97.83	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.67885958
94.57	0.08	94.31	0.19	91.84	0.16	93.09	0.00			93.85	0.11	96.50	0.00	97.83	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1675550831
94.63	0.07	94.31	0.00	91.84	0.00	93.49	0.40			93.85	0.00	96.50	0.00	97.83	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.838181758
94.70	0.06	94.31	0.00	92.01	0.17	93.50	0.02			94.04	0.19	96.50	0.00	97.83	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1716518746
94.76	0.06	94.31	0.00	92.01	0.00	93.50	0.00			94.04	0.00	96.50	0.00	98.19	0.36	/workspace/coverage/cover_reg_top/19.xbar_access_same_device.455539635
94.81	0.06	94.31	0.00	92.02	0.01	93.83	0.33			94.04	0.00	96.50	0.00	98.19	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3617721011
94.87	0.05	94.31	0.00	92.04	0.02	94.13	0.30			94.04	0.00	96.50	0.00	98.19	0.00	/workspace/coverage/cover_reg_top/71.xbar_same_source.622745584
94.92	0.05	94.37	0.07	92.06	0.02	94.14	0.01			94.07	0.02	96.68	0.17	98.20	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.773247225
94.97	0.05	94.38	0.01	92.09	0.03	94.19	0.05			94.08	0.02	96.85	0.17	98.20	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3549101234
95.01	0.04	94.39	0.01	92.10	0.01	94.19	0.01			94.11	0.02	97.03	0.17	98.21	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765095577
95.04	0.04	94.39	0.00	92.10	0.00	94.42	0.23			94.11	0.00	97.03	0.00	98.21	0.00	/workspace/coverage/default/1.chip_sw_flash_init.1273759530
95.08	0.04	94.40	0.01	92.11	0.01	94.43	0.01			94.12	0.01	97.20	0.17	98.23	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3286080160
95.12	0.04	94.40	0.01	92.12	0.01	94.44	0.01			94.12	0.01	97.38	0.17	98.24	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.412440920
95.15	0.03	94.40	0.00	92.23	0.11	94.44	0.00			94.16	0.03	97.38	0.00	98.31	0.07	/workspace/coverage/cover_reg_top/52.xbar_stress_all.3359318140
95.18	0.03	94.40	0.00	92.23	0.00	94.63	0.20			94.16	0.00	97.38	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3544671475
95.21	0.03	94.40	0.00	92.23	0.01	94.64	0.01			94.16	0.00	97.55	0.17	98.31	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1390969080
95.24	0.03	94.40	0.00	92.38	0.15	94.64	0.00			94.16	0.00	97.55	0.00	98.32	0.01	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1232329408
95.27	0.03	94.40	0.00	92.50	0.11	94.64	0.00			94.19	0.03	97.55	0.00	98.33	0.01	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.509375832
95.29	0.02	94.47	0.07	92.54	0.05	94.64	0.00			94.22	0.03	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4223627002
95.32	0.02	94.51	0.04	92.58	0.04	94.66	0.02			94.26	0.04	97.55	0.00	98.34	0.01	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2291362925
95.34	0.02	94.58	0.07	92.58	0.00	94.73	0.07			94.27	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2837380523
95.37	0.02	94.61	0.03	92.62	0.04	94.78	0.05			94.30	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1760425723
95.39	0.02	94.65	0.04	92.67	0.05	94.78	0.01			94.34	0.04	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.316278713
95.41	0.02	94.72	0.07	92.72	0.05	94.78	0.01			94.35	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2535849613
95.43	0.02	94.78	0.07	92.77	0.05	94.78	0.00			94.37	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4043010367
95.46	0.02	94.78	0.00	92.90	0.13	94.78	0.00			94.37	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3388857338
95.47	0.02	94.78	0.00	92.90	0.00	94.90	0.12			94.37	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1118183794
95.49	0.02	94.80	0.02	92.99	0.09	94.90	0.00			94.37	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2883843694
95.51	0.02	94.80	0.00	92.99	0.00	94.90	0.00			94.37	0.00	97.55	0.00	98.45	0.11	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2014852232
95.53	0.02	94.80	0.00	92.99	0.00	95.01	0.11			94.37	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1082429170
95.54	0.01	94.80	0.00	93.08	0.09	95.01	0.00			94.37	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1798773163
95.56	0.01	94.80	0.00	93.10	0.01	95.01	0.00			94.37	0.00	97.55	0.00	98.52	0.07	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.992468258
95.57	0.01	94.80	0.00	93.13	0.04	95.01	0.00			94.37	0.00	97.55	0.00	98.57	0.05	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.479712288
95.58	0.01	94.80	0.00	93.13	0.00	95.01	0.00			94.37	0.00	97.55	0.00	98.64	0.07	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2526710316
95.59	0.01	94.80	0.00	93.19	0.06	95.01	0.00			94.37	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1796254269
95.60	0.01	94.80	0.00	93.24	0.05	95.01	0.00			94.37	0.00	97.55	0.00	98.65	0.01	/workspace/coverage/cover_reg_top/29.chip_tl_errors.150899612
95.61	0.01	94.82	0.02	93.25	0.01	95.03	0.03			94.37	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.3066291291
95.62	0.01	94.82	0.00	93.25	0.00	95.09	0.06			94.37	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.405995620
95.63	0.01	94.82	0.00	93.25	0.00	95.14	0.05			94.37	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1250162795
95.64	0.01	94.84	0.02	93.26	0.01	95.14	0.01			94.38	0.02	97.55	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.322033160
95.65	0.01	94.87	0.02	93.27	0.01	95.14	0.01			94.40	0.02	97.55	0.00	98.65	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4114095986
95.65	0.01	94.87	0.00	93.27	0.00	95.19	0.05			94.40	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2010063750
95.66	0.01	94.87	0.01	93.28	0.01	95.20	0.01			94.42	0.02	97.55	0.00	98.65	0.00	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3115870504
95.67	0.01	94.89	0.02	93.28	0.00	95.22	0.02			94.42	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4229781347
95.67	0.01	94.89	0.00	93.31	0.04	95.22	0.00			94.42	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.1187962238
95.68	0.01	94.89	0.00	93.35	0.04	95.22	0.00			94.42	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3116642977
95.69	0.01	94.89	0.00	93.38	0.04	95.22	0.00			94.42	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3862300246
95.69	0.01	94.89	0.00	93.38	0.00	95.22	0.00			94.42	0.00	97.55	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.967964892
95.70	0.01	94.89	0.00	93.38	0.00	95.22	0.00			94.42	0.00	97.55	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2089741654
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95.92	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.688724879
95.92	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799160314
95.92	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.4245338454
95.92	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.2565915963
95.92	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.59	0.01	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1119679815
95.93	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.60	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3822564109
95.93	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.61	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770586799
95.93	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.62	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1630131807
95.93	0.01	94.91	0.00	93.65	0.00	95.39	0.00			94.44	0.00	97.55	0.00	99.64	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4255447765
95.93	0.01	94.91	0.00	93.66	0.01	95.40	0.01			94.44	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc.123151119
95.93	0.01	94.91	0.00	93.66	0.00	95.41	0.01			94.44	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.563987199
95.94	0.01	94.91	0.00	93.67	0.01	95.41	0.00			94.44	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.765475747
95.94	0.01	94.92	0.01	93.67	0.00	95.42	0.01			94.44	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2194760267
95.94	0.01	94.92	0.00	93.67	0.00	95.43	0.01			94.44	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3021088800
95.94	0.01	94.92	0.00	93.67	0.00	95.43	0.00			94.45	0.01	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2191091651
95.94	0.01	94.92	0.00	93.67	0.00	95.43	0.00			94.46	0.01	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2325210395
95.94	0.01	94.92	0.00	93.67	0.00	95.43	0.00			94.47	0.01	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.1902458670
95.95	0.01	94.92	0.00	93.67	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_rw.847924782
95.95	0.01	94.92	0.00	93.68	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1441150886
95.95	0.01	94.92	0.00	93.69	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4009196555
95.95	0.01	94.92	0.00	93.70	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.115553092
95.95	0.01	94.92	0.00	93.70	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/1.chip_sw_gpio.2387709142
95.95	0.01	94.92	0.00	93.71	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/2.chip_sw_gpio.2380463297
95.95	0.01	94.92	0.00	93.72	0.01	95.43	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1736781500
95.95	0.01	94.92	0.00	93.72	0.00	95.43	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1770216852
95.95	0.01	94.92	0.00	93.72	0.00	95.44	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1376522788
95.96	0.01	94.92	0.00	93.72	0.00	95.45	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2938611975
95.96	0.01	94.92	0.01	93.72	0.01	95.45	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3389869488
95.96	0.01	94.93	0.01	93.72	0.00	95.45	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3424004691
95.96	0.01	94.93	0.01	93.72	0.00	95.45	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1826084259
95.96	0.01	94.94	0.01	93.72	0.00	95.45	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.2550396344
95.96	0.01	94.94	0.00	93.72	0.00	95.45	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1338810578
95.96	0.01	94.94	0.00	93.72	0.00	95.46	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1036692768
95.96	0.01	94.94	0.00	93.72	0.00	95.46	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.870041603
95.96	0.01	94.94	0.00	93.72	0.00	95.47	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3614829179
95.96	0.01	94.94	0.00	93.72	0.00	95.47	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3785010993
95.96	0.01	94.94	0.00	93.72	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2635471587
95.97	0.01	94.94	0.00	93.73	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.169547503
95.97	0.01	94.94	0.00	93.73	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.665772997
95.97	0.01	94.94	0.00	93.73	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2773487361
95.97	0.01	94.94	0.00	93.74	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1536300214
95.97	0.01	94.94	0.00	93.74	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3943941822
95.97	0.01	94.94	0.00	93.75	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1488594948
95.97	0.01	94.94	0.00	93.75	0.01	95.47	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.981235831
95.97	0.01	94.94	0.00	93.75	0.00	95.48	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3599110215
95.97	0.01	94.94	0.01	93.75	0.00	95.48	0.00			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2830251761
95.97	0.01	94.94	0.00	93.75	0.00	95.48	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.48476312
95.97	0.01	94.94	0.00	93.75	0.00	95.48	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1049201136
95.97	0.01	94.94	0.00	93.75	0.00	95.48	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.772426290
95.97	0.01	94.94	0.00	93.75	0.00	95.48	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1029818254
95.97	0.01	94.94	0.00	93.75	0.00	95.49	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2227168155
95.97	0.01	94.94	0.00	93.75	0.00	95.49	0.01			94.47	0.00	97.55	0.00	99.64	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1830056137

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.4046830406
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3984450969
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1689646165
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4094389622
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1003594105
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1234193770
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2637075141
/workspace/coverage/cover_reg_top/0.xbar_error_random.2151329036
/workspace/coverage/cover_reg_top/0.xbar_random.3215316059
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2753246350
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2353378827
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.365419809
/workspace/coverage/cover_reg_top/0.xbar_same_source.4052393558
/workspace/coverage/cover_reg_top/0.xbar_smoke.3191756661
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4115693731
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.836333180
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.601090733
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2970549004
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.813258761
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4016756885
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1749839065
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4293579953
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2023702
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.579469673
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1060870122
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1182916935
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3867937832
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2037750833
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4957950
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1619802508
/workspace/coverage/cover_reg_top/1.xbar_error_random.993691807
/workspace/coverage/cover_reg_top/1.xbar_random.3011597466
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1130564059
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3709991677
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2613018399
/workspace/coverage/cover_reg_top/1.xbar_same_source.686785092
/workspace/coverage/cover_reg_top/1.xbar_smoke.114317936
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2249921969
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2178730070
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2711793081
/workspace/coverage/cover_reg_top/1.xbar_stress_all.294701708
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.707300164
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.991334029
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1860077239
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4219438245
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.851301337
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2122188144
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1703895272
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1545781903
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1548335805
/workspace/coverage/cover_reg_top/10.xbar_error_random.3611302647
/workspace/coverage/cover_reg_top/10.xbar_random.3509626662
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3818240112
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1835331035
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.695443034
/workspace/coverage/cover_reg_top/10.xbar_same_source.2504254394
/workspace/coverage/cover_reg_top/10.xbar_smoke.3459584676
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1613693110
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.4152994064
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3166608094
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3416115532
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1407778363
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3813405758
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4002904633
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2421545682
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.822129189
/workspace/coverage/cover_reg_top/11.chip_tl_errors.4132546014
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2722360400
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1034266400
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2648680247
/workspace/coverage/cover_reg_top/11.xbar_error_random.105384192
/workspace/coverage/cover_reg_top/11.xbar_random.3108970995
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3415217688
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3234089684
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.474345818
/workspace/coverage/cover_reg_top/11.xbar_same_source.1942327941
/workspace/coverage/cover_reg_top/11.xbar_smoke.845365766
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.22711982
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.792839184
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.211620782
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3060340411
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.165750587
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3845069929
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3705027616
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3601594068
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.24903904
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2070104010
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2156840115
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2394104688
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3594451761
/workspace/coverage/cover_reg_top/12.xbar_error_random.238056673
/workspace/coverage/cover_reg_top/12.xbar_random.3985880805
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3474734513
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2989645248
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3130562187
/workspace/coverage/cover_reg_top/12.xbar_same_source.2200315386
/workspace/coverage/cover_reg_top/12.xbar_smoke.936665557
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2917914486
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.565231197
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3429738265
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1419075985
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3346435461
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2252111826
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.578499794
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3946635365
/workspace/coverage/cover_reg_top/13.chip_csr_rw.161847493
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3159171377
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3949795998
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.909610135
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1325587640
/workspace/coverage/cover_reg_top/13.xbar_error_random.3751253303
/workspace/coverage/cover_reg_top/13.xbar_random.3814076068
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3363534042
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4072295076
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.479321496
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/workspace/coverage/default/2.chip_sw_rv_timer_irq.3209086383
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/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3073564974
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2962417041
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1044399337
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1442110958
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3889995049
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.977212843
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/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2554568027
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/workspace/coverage/default/3.chip_tap_straps_dev.3621364104
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/workspace/coverage/default/3.chip_tap_straps_rma.628806790
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3104329242
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2181704424
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.388379002
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1129908103
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2104891714
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039300761
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3369591783
/workspace/coverage/default/38.chip_sw_all_escalation_resets.479341309
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870444632
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3918791693
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.430072706
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2101571746
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2819095815
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.470398753
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1978778407
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2779999275
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.737110222
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4035596340
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2431421647
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.3118056920
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2539111775
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/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3257352277
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2431005709
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.758015860
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1432111407
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.290601944
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1189503749
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.339345414
/workspace/coverage/default/47.chip_sw_all_escalation_resets.4205026526
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3101092190
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.171691329
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1971215639
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1173857747
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1778687667
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1264621288
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.296886248
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.4070928608
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193603827
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3859214234
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1041439104
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3334659763
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137097537
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4163511877
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3011163767
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3277448936
/workspace/coverage/default/56.chip_sw_all_escalation_resets.643269630
/workspace/coverage/default/57.chip_sw_all_escalation_resets.31251906
/workspace/coverage/default/58.chip_sw_all_escalation_resets.835991907
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.916803752
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3391817831
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489048446
/workspace/coverage/default/6.chip_sw_all_escalation_resets.463001075
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2064579477
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.653596562
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3459549660
/workspace/coverage/default/60.chip_sw_all_escalation_resets.302465254
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2091589551
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.202387463
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2356599338
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293156308
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3216812904
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304534209
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2769448665
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4121208526
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4134016539
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510892128
/workspace/coverage/default/67.chip_sw_all_escalation_resets.525612349
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438872128
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4176624222
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745409523
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1574291702
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2425085222
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.302332853
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3100173389
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2700281374
/workspace/coverage/default/71.chip_sw_all_escalation_resets.974976635
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702989085
/workspace/coverage/default/72.chip_sw_all_escalation_resets.535754386
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.368360708
/workspace/coverage/default/73.chip_sw_all_escalation_resets.4235608806
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.777981736
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1205264741
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688346360
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1358300085
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1195968722
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1390157813
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1923686697
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2354696544
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3305371268
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3071291468
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3825901339
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3279601678
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015914767
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2583594032
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2460096381
/workspace/coverage/default/83.chip_sw_all_escalation_resets.325581307
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2780484339
/workspace/coverage/default/84.chip_sw_all_escalation_resets.840751994
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.710346718
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2602857825
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671529038
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1634686356
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.882890145
/workspace/coverage/default/87.chip_sw_all_escalation_resets.441650846
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.239285501
/workspace/coverage/default/88.chip_sw_all_escalation_resets.934182992
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029169205
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3951678208
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2040039149
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2831828749
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1715281258
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1614681104
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2046112133
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3115017885
/workspace/coverage/default/93.chip_sw_all_escalation_resets.521100630
/workspace/coverage/default/94.chip_sw_all_escalation_resets.950524619
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3106687411
/workspace/coverage/default/97.chip_sw_all_escalation_resets.4101108586
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3259080473
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1360865640
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3039733768
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.455431039
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.369083678
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2725108361
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2908630541
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2213339089
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3370136200

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Total test records in report: 2896

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_flash_init.1273759530			Jun 11 04:06:34 PM PDT 24	Jun 11 04:40:19 PM PDT 24	24459394835 ps
T5	/workspace/coverage/default/1.chip_sw_spi_device_tpm.2420096419			Jun 11 04:08:21 PM PDT 24	Jun 11 04:16:33 PM PDT 24	3484018886 ps
T6	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1802642830			Jun 11 04:12:01 PM PDT 24	Jun 11 04:18:11 PM PDT 24	6244619352 ps
T62	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2669350484			Jun 11 04:20:48 PM PDT 24	Jun 11 04:25:06 PM PDT 24	3112907416 ps
T16	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3464728593			Jun 11 04:24:38 PM PDT 24	Jun 11 04:49:44 PM PDT 24	8254016120 ps
T17	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4236347694			Jun 11 04:17:20 PM PDT 24	Jun 11 04:30:30 PM PDT 24	3489395356 ps
T41	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1166641058			Jun 11 04:24:22 PM PDT 24	Jun 11 04:35:31 PM PDT 24	6049360656 ps
T56	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1250162795			Jun 11 04:21:18 PM PDT 24	Jun 11 04:32:12 PM PDT 24	3915558760 ps
T83	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1706144229			Jun 11 04:00:30 PM PDT 24	Jun 11 04:10:07 PM PDT 24	3928350572 ps
T52	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1084373574			Jun 11 04:09:19 PM PDT 24	Jun 11 05:07:48 PM PDT 24	14515205688 ps
T58	/workspace/coverage/default/2.chip_sw_alert_test.1327823568			Jun 11 04:20:15 PM PDT 24	Jun 11 04:27:26 PM PDT 24	3913737510 ps
T27	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.925960237			Jun 11 04:24:13 PM PDT 24	Jun 11 04:32:27 PM PDT 24	6172943880 ps
T53	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3034642076			Jun 11 04:27:09 PM PDT 24	Jun 11 05:21:15 PM PDT 24	15062134738 ps
T134	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2793300966			Jun 11 04:04:12 PM PDT 24	Jun 11 04:08:16 PM PDT 24	3336705801 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1630444635			Jun 11 04:04:24 PM PDT 24	Jun 11 04:42:18 PM PDT 24	22810348836 ps
T96	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1359566830			Jun 11 04:09:32 PM PDT 24	Jun 11 04:12:53 PM PDT 24	3094990184 ps
T97	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564323289			Jun 11 04:31:20 PM PDT 24	Jun 11 04:39:01 PM PDT 24	3456238780 ps
T65	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3785010993			Jun 11 03:59:30 PM PDT 24	Jun 11 04:10:07 PM PDT 24	7531727092 ps
T98	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770586799			Jun 11 04:26:55 PM PDT 24	Jun 11 04:33:11 PM PDT 24	3585596168 ps
T99	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1685555913			Jun 11 04:05:00 PM PDT 24	Jun 11 04:09:15 PM PDT 24	2696830085 ps
T100	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4108100968			Jun 11 04:10:22 PM PDT 24	Jun 11 04:40:37 PM PDT 24	8663822000 ps
T101	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1050619913			Jun 11 04:19:38 PM PDT 24	Jun 11 06:16:28 PM PDT 24	29014058952 ps
T2	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2535849613			Jun 11 04:08:21 PM PDT 24	Jun 11 04:12:37 PM PDT 24	3024285064 ps
T102	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3450750837			Jun 11 04:06:28 PM PDT 24	Jun 11 04:11:09 PM PDT 24	2864153844 ps
T63	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1971215639			Jun 11 04:25:11 PM PDT 24	Jun 11 04:35:50 PM PDT 24	5005605550 ps
T202	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.720748910			Jun 11 04:26:51 PM PDT 24	Jun 11 04:55:39 PM PDT 24	8351053092 ps
T118	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3378026961			Jun 11 04:04:56 PM PDT 24	Jun 11 04:14:30 PM PDT 24	5133372126 ps
T197	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2843263590			Jun 11 04:18:11 PM PDT 24	Jun 11 04:22:28 PM PDT 24	2714304628 ps
T400	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.436874898			Jun 11 04:03:20 PM PDT 24	Jun 11 04:09:09 PM PDT 24	2441446100 ps
T148	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4093990956			Jun 11 03:59:52 PM PDT 24	Jun 11 04:03:43 PM PDT 24	2463139248 ps
T233	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2474134795			Jun 11 04:29:07 PM PDT 24	Jun 11 04:38:45 PM PDT 24	4005441584 ps
T18	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2385927138			Jun 11 04:09:28 PM PDT 24	Jun 11 05:10:52 PM PDT 24	13452869037 ps
T57	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.633038292			Jun 11 04:14:10 PM PDT 24	Jun 11 04:25:53 PM PDT 24	3777321536 ps
T28	/workspace/coverage/default/0.chip_sw_usbdev_dpi.2597593438			Jun 11 03:59:26 PM PDT 24	Jun 11 04:53:07 PM PDT 24	12432467892 ps
T25	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1542761251			Jun 11 04:07:33 PM PDT 24	Jun 11 04:49:48 PM PDT 24	12562785840 ps
T291	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2780484339			Jun 11 04:35:44 PM PDT 24	Jun 11 04:43:58 PM PDT 24	4532832060 ps
T64	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2291362925			Jun 11 04:11:30 PM PDT 24	Jun 11 04:43:58 PM PDT 24	13227197652 ps
T54	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3617721011			Jun 11 03:59:05 PM PDT 24	Jun 11 04:01:30 PM PDT 24	3380418524 ps
T153	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765095577			Jun 11 04:30:29 PM PDT 24	Jun 11 04:41:03 PM PDT 24	3777697320 ps
T292	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3459549660			Jun 11 04:31:33 PM PDT 24	Jun 11 04:39:04 PM PDT 24	4567068106 ps
T55	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1563623647			Jun 11 04:01:24 PM PDT 24	Jun 11 05:48:47 PM PDT 24	47023624400 ps
T160	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.806325737			Jun 11 04:27:33 PM PDT 24	Jun 11 05:06:27 PM PDT 24	10766265849 ps
T182	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3967524225			Jun 11 04:11:14 PM PDT 24	Jun 11 05:03:50 PM PDT 24	34437860051 ps
T110	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.961552867			Jun 11 04:04:02 PM PDT 24	Jun 11 04:07:03 PM PDT 24	3033520749 ps
T241	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1925466826			Jun 11 04:09:20 PM PDT 24	Jun 11 04:18:25 PM PDT 24	3849281112 ps
T59	/workspace/coverage/default/0.chip_sw_alert_test.3929635796			Jun 11 04:02:37 PM PDT 24	Jun 11 04:07:33 PM PDT 24	3405963840 ps
T72	/workspace/coverage/default/3.chip_tap_straps_prod.3226226358			Jun 11 04:24:09 PM PDT 24	Jun 11 04:39:46 PM PDT 24	11205285914 ps
T163	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3889995049			Jun 11 04:20:21 PM PDT 24	Jun 11 04:33:04 PM PDT 24	8396846008 ps
T29	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2812645314			Jun 11 04:00:33 PM PDT 24	Jun 11 04:37:41 PM PDT 24	22970105904 ps
T173	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2941105662			Jun 11 04:09:22 PM PDT 24	Jun 11 04:30:41 PM PDT 24	13045355606 ps
T22	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2534751856			Jun 11 04:08:25 PM PDT 24	Jun 11 04:23:41 PM PDT 24	8053844120 ps
T854	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2230397894			Jun 11 04:17:55 PM PDT 24	Jun 11 04:23:20 PM PDT 24	2731112604 ps
T26	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.655119720			Jun 11 04:16:51 PM PDT 24	Jun 11 04:30:24 PM PDT 24	4888542905 ps
T234	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1666256193			Jun 11 04:30:38 PM PDT 24	Jun 11 04:41:58 PM PDT 24	4726763510 ps
T142	/workspace/coverage/default/2.chip_sw_power_idle_load.516185104			Jun 11 04:23:30 PM PDT 24	Jun 11 04:33:58 PM PDT 24	4173193698 ps
T157	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2555362215			Jun 11 04:07:58 PM PDT 24	Jun 11 05:42:10 PM PDT 24	51433158995 ps
T620	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2246443657			Jun 11 04:09:05 PM PDT 24	Jun 11 04:15:24 PM PDT 24	3926173492 ps
T165	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1393165749			Jun 11 04:24:14 PM PDT 24	Jun 11 04:30:37 PM PDT 24	3446580462 ps
T296	/workspace/coverage/default/0.chip_sw_hmac_enc.2501931917			Jun 11 04:02:25 PM PDT 24	Jun 11 04:06:36 PM PDT 24	2669909592 ps
T297	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4268496277			Jun 11 04:16:53 PM PDT 24	Jun 11 04:20:24 PM PDT 24	2603533936 ps
T50	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3400592281			Jun 11 04:11:23 PM PDT 24	Jun 11 05:36:53 PM PDT 24	22415517563 ps
T298	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.520026290			Jun 11 04:01:38 PM PDT 24	Jun 11 04:05:10 PM PDT 24	3374488280 ps
T115	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4276029213			Jun 11 04:02:02 PM PDT 24	Jun 11 04:47:57 PM PDT 24	12782048176 ps
T299	/workspace/coverage/default/2.chip_sw_aes_smoketest.2249429932			Jun 11 04:24:50 PM PDT 24	Jun 11 04:29:47 PM PDT 24	3194892984 ps
T300	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1931857774			Jun 11 04:16:28 PM PDT 24	Jun 11 05:20:49 PM PDT 24	14730315927 ps
T301	/workspace/coverage/default/0.chip_sw_hmac_multistream.1151124224			Jun 11 04:03:42 PM PDT 24	Jun 11 04:27:51 PM PDT 24	6185138146 ps
T103	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1376522788			Jun 11 04:02:37 PM PDT 24	Jun 11 04:12:16 PM PDT 24	19877663814 ps
T30	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.436497402			Jun 11 04:08:46 PM PDT 24	Jun 11 04:14:48 PM PDT 24	3469453370 ps
T3	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.16881466			Jun 11 04:22:21 PM PDT 24	Jun 11 04:43:47 PM PDT 24	22563878344 ps
T207	/workspace/coverage/default/46.chip_sw_all_escalation_resets.773247225			Jun 11 04:31:29 PM PDT 24	Jun 11 04:41:50 PM PDT 24	4482761608 ps
T158	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.945103717			Jun 11 04:11:22 PM PDT 24	Jun 11 05:36:50 PM PDT 24	49641337965 ps
T253	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.135230184			Jun 11 04:10:55 PM PDT 24	Jun 11 06:02:33 PM PDT 24	23083580980 ps
T254	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2629963045			Jun 11 04:10:52 PM PDT 24	Jun 11 04:54:18 PM PDT 24	11217662592 ps
T208	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2755634878			Jun 11 04:32:41 PM PDT 24	Jun 11 04:42:18 PM PDT 24	4228967588 ps
T255	/workspace/coverage/default/2.chip_sw_hmac_multistream.1218232075			Jun 11 04:19:08 PM PDT 24	Jun 11 04:43:54 PM PDT 24	7154709740 ps
T203	/workspace/coverage/default/1.chip_sw_uart_tx_rx.3890084210			Jun 11 04:07:02 PM PDT 24	Jun 11 04:18:53 PM PDT 24	4748952122 ps
T228	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1954410586			Jun 11 04:17:42 PM PDT 24	Jun 11 04:30:17 PM PDT 24	5670851496 ps
T256	/workspace/coverage/default/0.rom_e2e_smoke.1769474198			Jun 11 04:08:45 PM PDT 24	Jun 11 05:11:14 PM PDT 24	14868145130 ps
T244	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3305371268			Jun 11 04:26:08 PM PDT 24	Jun 11 06:05:56 PM PDT 24	29000376650 ps
T855	/workspace/coverage/default/1.chip_sw_example_concurrency.3736402411			Jun 11 04:06:19 PM PDT 24	Jun 11 04:09:10 PM PDT 24	1989596240 ps
T140	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1760425723			Jun 11 04:09:09 PM PDT 24	Jun 11 04:39:07 PM PDT 24	7628432003 ps
T856	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3840102609			Jun 11 04:16:54 PM PDT 24	Jun 11 04:21:03 PM PDT 24	3220281489 ps
T857	/workspace/coverage/default/1.chip_sw_csrng_smoketest.3496080331			Jun 11 04:14:38 PM PDT 24	Jun 11 04:18:17 PM PDT 24	2750841440 ps
T230	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2227168155			Jun 11 04:13:21 PM PDT 24	Jun 11 04:15:52 PM PDT 24	2456041240 ps
T7	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1675550831			Jun 11 04:15:55 PM PDT 24	Jun 11 04:20:33 PM PDT 24	2661854962 ps
T345	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2181704424			Jun 11 04:30:25 PM PDT 24	Jun 11 04:38:11 PM PDT 24	4576998528 ps
T201	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1751740438			Jun 11 04:05:35 PM PDT 24	Jun 11 04:28:35 PM PDT 24	9395292732 ps
T238	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2489948087			Jun 11 04:09:25 PM PDT 24	Jun 11 04:14:43 PM PDT 24	3253859196 ps
T152	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1432111407			Jun 11 04:29:55 PM PDT 24	Jun 11 04:38:49 PM PDT 24	5969907984 ps
T164	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.846624186			Jun 11 04:00:32 PM PDT 24	Jun 11 04:07:52 PM PDT 24	8223046040 ps
T384	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.471294972			Jun 11 04:30:51 PM PDT 24	Jun 11 04:36:36 PM PDT 24	3880802668 ps
T112	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3320189145			Jun 11 04:03:09 PM PDT 24	Jun 11 04:15:27 PM PDT 24	5576540986 ps
T338	/workspace/coverage/default/94.chip_sw_all_escalation_resets.950524619			Jun 11 04:34:55 PM PDT 24	Jun 11 04:44:57 PM PDT 24	4701800760 ps
T385	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.4148088671			Jun 11 04:13:05 PM PDT 24	Jun 11 04:18:17 PM PDT 24	3215337014 ps
T628	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.317511582			Jun 11 04:20:13 PM PDT 24	Jun 11 04:37:28 PM PDT 24	7079378428 ps
T239	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.658364969			Jun 11 04:25:38 PM PDT 24	Jun 11 04:29:45 PM PDT 24	3044968936 ps
T69	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1985655183			Jun 11 04:06:16 PM PDT 24	Jun 11 04:50:29 PM PDT 24	13881633674 ps
T339	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2503547397			Jun 11 04:26:52 PM PDT 24	Jun 11 04:38:39 PM PDT 24	4684953022 ps
T858	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4172387234			Jun 11 04:03:02 PM PDT 24	Jun 11 04:11:46 PM PDT 24	4714251304 ps
T637	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4124384846			Jun 11 04:19:18 PM PDT 24	Jun 11 04:27:09 PM PDT 24	5192564448 ps
T859	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1438216147			Jun 11 04:14:45 PM PDT 24	Jun 11 04:25:01 PM PDT 24	3702178332 ps
T61	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.316278713			Jun 11 04:01:00 PM PDT 24	Jun 11 04:09:54 PM PDT 24	3831333772 ps
T51	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3702824576			Jun 11 04:13:29 PM PDT 24	Jun 11 05:24:26 PM PDT 24	13843388602 ps
T860	/workspace/coverage/default/1.chip_sw_kmac_smoketest.4018552886			Jun 11 04:16:51 PM PDT 24	Jun 11 04:22:10 PM PDT 24	3330194672 ps
T107	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.150718659			Jun 11 04:14:32 PM PDT 24	Jun 11 04:34:55 PM PDT 24	8561937629 ps
T638	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1195968722			Jun 11 04:32:10 PM PDT 24	Jun 11 04:41:08 PM PDT 24	6276505240 ps
T861	/workspace/coverage/default/0.chip_sw_edn_sw_mode.390679903			Jun 11 04:02:42 PM PDT 24	Jun 11 04:25:06 PM PDT 24	7152278132 ps
T229	/workspace/coverage/default/64.chip_sw_all_escalation_resets.2769448665			Jun 11 04:31:08 PM PDT 24	Jun 11 04:39:43 PM PDT 24	5905154526 ps
T862	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1605678022			Jun 11 04:25:05 PM PDT 24	Jun 11 04:34:12 PM PDT 24	4385614192 ps
T135	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4267927014			Jun 11 04:12:33 PM PDT 24	Jun 11 04:15:31 PM PDT 24	2552194680 ps
T204	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2654385210			Jun 11 03:59:01 PM PDT 24	Jun 11 04:11:40 PM PDT 24	4485173798 ps
T304	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2956349982			Jun 11 04:30:29 PM PDT 24	Jun 11 04:41:36 PM PDT 24	6573027800 ps
T141	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3359069913			Jun 11 04:24:31 PM PDT 24	Jun 11 04:57:12 PM PDT 24	8878575708 ps
T200	/workspace/coverage/default/1.chip_sw_pattgen_ios.74395596			Jun 11 04:06:13 PM PDT 24	Jun 11 04:09:41 PM PDT 24	2460034944 ps
T245	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.373256877			Jun 11 04:12:01 PM PDT 24	Jun 11 05:30:01 PM PDT 24	21047405344 ps
T863	/workspace/coverage/default/2.rom_e2e_static_critical.2536885370			Jun 11 04:27:28 PM PDT 24	Jun 11 05:20:50 PM PDT 24	16155945656 ps
T34	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1103950889			Jun 11 04:15:56 PM PDT 24	Jun 11 04:21:11 PM PDT 24	2693265188 ps
T226	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3745048706			Jun 11 04:01:27 PM PDT 24	Jun 11 04:10:15 PM PDT 24	3204306728 ps
T205	/workspace/coverage/default/0.chip_tap_straps_prod.447294486			Jun 11 04:03:49 PM PDT 24	Jun 11 04:06:19 PM PDT 24	2181568643 ps
T279	/workspace/coverage/default/1.chip_sw_all_escalation_resets.449653794			Jun 11 04:14:35 PM PDT 24	Jun 11 04:23:47 PM PDT 24	4878631364 ps
T280	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1777716307			Jun 11 04:24:53 PM PDT 24	Jun 11 05:29:38 PM PDT 24	15873035112 ps
T174	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1118183794			Jun 11 04:00:47 PM PDT 24	Jun 11 05:33:55 PM PDT 24	48455217096 ps
T281	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1691034103			Jun 11 04:10:50 PM PDT 24	Jun 11 04:21:24 PM PDT 24	6167272722 ps
T246	/workspace/coverage/default/4.chip_sw_all_escalation_resets.438106941			Jun 11 04:24:07 PM PDT 24	Jun 11 04:35:00 PM PDT 24	4691055346 ps
T282	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4155030206			Jun 11 04:10:20 PM PDT 24	Jun 11 04:22:16 PM PDT 24	5282940526 ps
T283	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4193608419			Jun 11 04:08:36 PM PDT 24	Jun 11 04:15:36 PM PDT 24	3611475820 ps
T284	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1929177386			Jun 11 04:12:50 PM PDT 24	Jun 11 04:22:37 PM PDT 24	4573905020 ps
T864	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3882990972			Jun 11 04:18:33 PM PDT 24	Jun 11 04:58:04 PM PDT 24	10942026512 ps
T257	/workspace/coverage/default/0.rom_volatile_raw_unlock.2403458545			Jun 11 04:06:47 PM PDT 24	Jun 11 04:08:46 PM PDT 24	2196484187 ps
T865	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2622064472			Jun 11 04:01:39 PM PDT 24	Jun 11 04:13:02 PM PDT 24	4443872744 ps
T171	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1456752875			Jun 11 04:19:46 PM PDT 24	Jun 11 04:28:18 PM PDT 24	3482917052 ps
T73	/workspace/coverage/default/2.chip_tap_straps_prod.1337428339			Jun 11 04:23:16 PM PDT 24	Jun 11 04:52:13 PM PDT 24	17199903798 ps
T258	/workspace/coverage/default/2.rom_volatile_raw_unlock.2933305538			Jun 11 04:23:21 PM PDT 24	Jun 11 04:25:37 PM PDT 24	2314350305 ps
T80	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1735593720			Jun 11 04:01:33 PM PDT 24	Jun 11 04:19:11 PM PDT 24	10636557780 ps
T227	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.4043733897			Jun 11 04:16:22 PM PDT 24	Jun 11 04:28:30 PM PDT 24	4891205396 ps
T265	/workspace/coverage/default/0.chip_sw_example_manufacturer.2331844809			Jun 11 03:59:35 PM PDT 24	Jun 11 04:03:51 PM PDT 24	2643335244 ps
T266	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1033930970			Jun 11 04:11:53 PM PDT 24	Jun 11 04:15:07 PM PDT 24	2856764706 ps
T267	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.37251167			Jun 11 04:10:01 PM PDT 24	Jun 11 04:34:40 PM PDT 24	7336695190 ps
T19	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1716518746			Jun 11 03:59:06 PM PDT 24	Jun 11 04:04:46 PM PDT 24	3038068419 ps
T268	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1776213338			Jun 11 04:27:12 PM PDT 24	Jun 11 04:35:21 PM PDT 24	4139577938 ps
T111	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3549101234			Jun 11 04:12:04 PM PDT 24	Jun 11 04:23:09 PM PDT 24	4776885204 ps
T269	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1182488210			Jun 11 04:30:09 PM PDT 24	Jun 11 04:37:54 PM PDT 24	3792562456 ps
T247	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3338488141			Jun 11 04:00:29 PM PDT 24	Jun 11 04:16:26 PM PDT 24	6743640408 ps
T270	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.290601944			Jun 11 04:30:24 PM PDT 24	Jun 11 04:36:18 PM PDT 24	3762522836 ps
T866	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.373002001			Jun 11 04:08:55 PM PDT 24	Jun 11 04:18:34 PM PDT 24	4744381826 ps
T231	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2707850261			Jun 11 04:08:53 PM PDT 24	Jun 11 04:35:56 PM PDT 24	10078092848 ps
T867	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2080224230			Jun 11 04:01:16 PM PDT 24	Jun 11 04:22:04 PM PDT 24	5138998367 ps
T20	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1122985311			Jun 11 04:08:07 PM PDT 24	Jun 11 04:13:23 PM PDT 24	3311645516 ps
T868	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3106687411			Jun 11 04:35:08 PM PDT 24	Jun 11 04:43:55 PM PDT 24	4779684980 ps
T337	/workspace/coverage/default/2.chip_sw_pattgen_ios.2550396344			Jun 11 04:15:11 PM PDT 24	Jun 11 04:18:41 PM PDT 24	2780433016 ps
T701	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039300761			Jun 11 04:29:33 PM PDT 24	Jun 11 04:35:20 PM PDT 24	3539076560 ps
T198	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3316354611			Jun 11 04:22:49 PM PDT 24	Jun 11 04:46:19 PM PDT 24	7104115264 ps
T210	/workspace/coverage/default/6.chip_sw_all_escalation_resets.463001075			Jun 11 04:25:45 PM PDT 24	Jun 11 04:37:57 PM PDT 24	6064540620 ps
T166	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3802561534			Jun 11 04:14:36 PM PDT 24	Jun 11 04:19:29 PM PDT 24	3373101818 ps
T690	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.388379002			Jun 11 04:33:03 PM PDT 24	Jun 11 04:39:33 PM PDT 24	3276492538 ps
T225	/workspace/coverage/default/1.rom_keymgr_functest.3083558760			Jun 11 04:15:47 PM PDT 24	Jun 11 04:27:27 PM PDT 24	4817599520 ps
T309	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.878281431			Jun 11 04:17:47 PM PDT 24	Jun 11 04:22:21 PM PDT 24	3052104619 ps
T240	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3209086383			Jun 11 04:19:32 PM PDT 24	Jun 11 04:25:47 PM PDT 24	3330589666 ps
T869	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3040236870			Jun 11 03:59:48 PM PDT 24	Jun 11 04:04:27 PM PDT 24	3357467638 ps
T870	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3606556973			Jun 11 04:01:11 PM PDT 24	Jun 11 04:07:22 PM PDT 24	3807701676 ps
T871	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1014979405			Jun 11 04:10:17 PM PDT 24	Jun 11 04:16:09 PM PDT 24	3261535152 ps
T872	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.306296142			Jun 11 04:18:13 PM PDT 24	Jun 11 04:27:58 PM PDT 24	6683199976 ps
T316	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.984189459			Jun 11 04:29:56 PM PDT 24	Jun 11 04:40:03 PM PDT 24	4526958052 ps
T873	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3623885421			Jun 11 04:03:05 PM PDT 24	Jun 11 04:06:09 PM PDT 24	2307617446 ps
T874	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3978924386			Jun 11 04:12:47 PM PDT 24	Jun 11 04:22:52 PM PDT 24	4811761664 ps
T697	/workspace/coverage/default/79.chip_sw_all_escalation_resets.2565915963			Jun 11 04:32:35 PM PDT 24	Jun 11 04:43:50 PM PDT 24	5632447600 ps
T136	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3021088800			Jun 11 04:01:08 PM PDT 24	Jun 11 04:07:22 PM PDT 24	9104616888 ps
T84	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4020365752			Jun 11 04:28:11 PM PDT 24	Jun 11 04:33:56 PM PDT 24	3805173784 ps
T88	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.164707592			Jun 11 04:15:28 PM PDT 24	Jun 11 04:20:56 PM PDT 24	2692767836 ps
T89	/workspace/coverage/default/2.chip_sw_edn_sw_mode.390352919			Jun 11 04:19:18 PM PDT 24	Jun 11 04:54:40 PM PDT 24	10052159988 ps
T90	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626927593			Jun 11 04:29:08 PM PDT 24	Jun 11 04:37:34 PM PDT 24	3388823892 ps
T91	/workspace/coverage/default/0.chip_sw_kmac_entropy.838181758			Jun 11 03:58:59 PM PDT 24	Jun 11 04:02:48 PM PDT 24	2812565400 ps
T45	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1625199137			Jun 11 04:11:41 PM PDT 24	Jun 11 04:17:47 PM PDT 24	6127047842 ps
T92	/workspace/coverage/default/2.chip_sw_edn_auto_mode.1597143542			Jun 11 04:19:12 PM PDT 24	Jun 11 04:31:26 PM PDT 24	3390182734 ps
T93	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.619815904			Jun 11 04:13:10 PM PDT 24	Jun 11 04:30:11 PM PDT 24	6673692182 ps
T70	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1521630442			Jun 11 04:16:37 PM PDT 24	Jun 11 04:26:44 PM PDT 24	4936061946 ps
T94	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3287231918			Jun 11 04:28:11 PM PDT 24	Jun 11 04:38:31 PM PDT 24	4958724292 ps
T875	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1817355078			Jun 11 04:14:49 PM PDT 24	Jun 11 04:19:08 PM PDT 24	2857970558 ps
T876	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3584737011			Jun 11 03:59:27 PM PDT 24	Jun 11 04:10:48 PM PDT 24	8400654940 ps
T340	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1527343069			Jun 11 04:30:14 PM PDT 24	Jun 11 04:40:35 PM PDT 24	5090746944 ps
T344	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4135605239			Jun 11 04:20:41 PM PDT 24	Jun 11 04:24:45 PM PDT 24	2291924669 ps
T212	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3529551854			Jun 11 04:00:25 PM PDT 24	Jun 11 04:23:58 PM PDT 24	8224059134 ps
T877	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1006250528			Jun 11 04:00:29 PM PDT 24	Jun 11 04:03:32 PM PDT 24	2551118707 ps
T878	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2440781170			Jun 11 04:08:05 PM PDT 24	Jun 11 04:14:02 PM PDT 24	2827450958 ps
T879	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3856674319			Jun 11 04:10:09 PM PDT 24	Jun 11 05:03:35 PM PDT 24	14425047470 ps
T764	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.191005388			Jun 11 04:28:40 PM PDT 24	Jun 11 04:35:26 PM PDT 24	4049062568 ps
T880	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3054152105			Jun 11 04:16:13 PM PDT 24	Jun 11 04:25:26 PM PDT 24	4145953776 ps
T881	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.114991002			Jun 11 04:11:51 PM PDT 24	Jun 11 04:17:33 PM PDT 24	3420375187 ps
T882	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1569764511			Jun 11 04:10:52 PM PDT 24	Jun 11 04:13:48 PM PDT 24	2095416540 ps
T343	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2962417041			Jun 11 04:22:09 PM PDT 24	Jun 11 04:27:28 PM PDT 24	3360680788 ps
T883	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1936512449			Jun 11 04:19:44 PM PDT 24	Jun 11 05:27:48 PM PDT 24	15619083040 ps
T190	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3910813417			Jun 11 04:10:02 PM PDT 24	Jun 11 04:15:33 PM PDT 24	3507491219 ps
T685	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3216812904			Jun 11 04:32:28 PM PDT 24	Jun 11 04:41:58 PM PDT 24	5256391832 ps
T884	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1763727672			Jun 11 04:07:34 PM PDT 24	Jun 11 04:28:59 PM PDT 24	8303087202 ps
T15	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4043010367			Jun 11 04:15:31 PM PDT 24	Jun 11 04:24:43 PM PDT 24	6360230644 ps
T388	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.645215454			Jun 11 04:18:20 PM PDT 24	Jun 11 05:43:44 PM PDT 24	15485768864 ps
T389	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2064579477			Jun 11 04:26:02 PM PDT 24	Jun 11 06:18:07 PM PDT 24	31863144860 ps
T81	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1574576760			Jun 11 04:10:18 PM PDT 24	Jun 11 04:33:48 PM PDT 24	11428016434 ps
T211	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3772020211			Jun 11 04:01:19 PM PDT 24	Jun 11 04:08:48 PM PDT 24	5666839200 ps
T113	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3725018620			Jun 11 04:01:43 PM PDT 24	Jun 11 04:27:39 PM PDT 24	7404553472 ps
T327	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4009196555			Jun 11 04:03:31 PM PDT 24	Jun 11 04:09:19 PM PDT 24	3709575276 ps
T390	/workspace/coverage/default/0.chip_sw_aes_entropy.1036568816			Jun 11 04:01:33 PM PDT 24	Jun 11 04:06:04 PM PDT 24	2788820952 ps
T235	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2539111775			Jun 11 04:31:43 PM PDT 24	Jun 11 04:38:12 PM PDT 24	3848557290 ps
T305	/workspace/coverage/default/2.chip_plic_all_irqs_20.1708783917			Jun 11 04:20:52 PM PDT 24	Jun 11 04:34:22 PM PDT 24	4655295340 ps
T885	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3481513390			Jun 11 04:27:02 PM PDT 24	Jun 11 04:39:46 PM PDT 24	9201124001 ps
T619	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600461822			Jun 11 04:30:13 PM PDT 24	Jun 11 04:35:39 PM PDT 24	3137685018 ps
T31	/workspace/coverage/default/2.chip_jtag_csr_rw.601481631			Jun 11 04:13:32 PM PDT 24	Jun 11 04:57:29 PM PDT 24	21657746403 ps
T886	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.737110222			Jun 11 04:25:07 PM PDT 24	Jun 11 04:35:07 PM PDT 24	3907116799 ps
T887	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1624341405			Jun 11 04:27:11 PM PDT 24	Jun 11 05:20:39 PM PDT 24	14220163792 ps
T888	/workspace/coverage/default/2.rom_e2e_asm_init_dev.3240079696			Jun 11 04:29:27 PM PDT 24	Jun 11 05:30:12 PM PDT 24	14979385107 ps
T82	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3451358641			Jun 11 04:19:12 PM PDT 24	Jun 11 04:39:52 PM PDT 24	12675357574 ps
T66	/workspace/coverage/default/4.chip_tap_straps_rma.3440801626			Jun 11 04:25:55 PM PDT 24	Jun 11 04:28:36 PM PDT 24	2599552081 ps
T889	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3406551280			Jun 11 04:23:49 PM PDT 24	Jun 11 04:29:53 PM PDT 24	3558534450 ps
T10	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2080151773			Jun 11 04:13:54 PM PDT 24	Jun 11 04:35:33 PM PDT 24	22697869200 ps
T108	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1538624571			Jun 11 04:05:17 PM PDT 24	Jun 11 04:38:00 PM PDT 24	12054740617 ps
T114	/workspace/coverage/default/1.chip_sw_edn_auto_mode.1876222205			Jun 11 04:11:33 PM PDT 24	Jun 11 04:41:26 PM PDT 24	5766846866 ps
T890	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2831828749			Jun 11 04:28:58 PM PDT 24	Jun 11 05:35:34 PM PDT 24	20853149744 ps
T891	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1697914221			Jun 11 04:29:07 PM PDT 24	Jun 11 04:42:52 PM PDT 24	13925571074 ps
T191	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3770678310			Jun 11 04:08:51 PM PDT 24	Jun 11 04:20:01 PM PDT 24	5109478901 ps
T682	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1756888106			Jun 11 04:13:38 PM PDT 24	Jun 11 04:22:42 PM PDT 24	3593591592 ps
T892	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3456332750			Jun 11 04:11:19 PM PDT 24	Jun 11 04:22:33 PM PDT 24	9915859560 ps
T259	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3399490172			Jun 11 04:10:46 PM PDT 24	Jun 11 05:27:27 PM PDT 24	13808343784 ps
T675	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4255447765			Jun 11 04:35:15 PM PDT 24	Jun 11 04:44:57 PM PDT 24	4906715336 ps
T893	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1752628882			Jun 11 04:08:38 PM PDT 24	Jun 11 04:22:07 PM PDT 24	4736415954 ps
T894	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2447542643			Jun 11 04:21:27 PM PDT 24	Jun 11 04:31:16 PM PDT 24	6786399159 ps
T32	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2964274644			Jun 11 04:01:10 PM PDT 24	Jun 11 05:57:17 PM PDT 24	31258029144 ps
T220	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2571334254			Jun 11 04:03:23 PM PDT 24	Jun 11 04:39:48 PM PDT 24	26374431385 ps
T46	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2631053516			Jun 11 04:01:13 PM PDT 24	Jun 11 04:08:53 PM PDT 24	4954915568 ps
T12	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.115553092			Jun 11 03:59:35 PM PDT 24	Jun 11 04:03:28 PM PDT 24	2946332188 ps
T213	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1082429170			Jun 11 04:00:51 PM PDT 24	Jun 11 05:03:28 PM PDT 24	13481412496 ps
T133	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3714442864			Jun 11 04:21:22 PM PDT 24	Jun 11 04:26:19 PM PDT 24	6216752104 ps
T262	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2104346427			Jun 11 04:02:54 PM PDT 24	Jun 11 04:07:22 PM PDT 24	2786250294 ps
T67	/workspace/coverage/default/1.chip_tap_straps_testunlock0.2127837545			Jun 11 04:13:03 PM PDT 24	Jun 11 04:22:40 PM PDT 24	5455306211 ps
T33	/workspace/coverage/default/0.chip_jtag_csr_rw.2094807833			Jun 11 03:55:12 PM PDT 24	Jun 11 04:00:44 PM PDT 24	4795271256 ps
T720	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2700281374			Jun 11 04:33:34 PM PDT 24	Jun 11 04:41:27 PM PDT 24	4299579400 ps
T242	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1243024876			Jun 11 04:22:06 PM PDT 24	Jun 11 04:33:35 PM PDT 24	4893381336 ps
T769	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1915853567			Jun 11 04:30:48 PM PDT 24	Jun 11 04:38:34 PM PDT 24	5337430320 ps
T724	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3755015674			Jun 11 04:29:07 PM PDT 24	Jun 11 04:35:45 PM PDT 24	4036231700 ps
T895	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.59158452			Jun 11 04:19:51 PM PDT 24	Jun 11 04:30:31 PM PDT 24	4252069162 ps
T896	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.667269955			Jun 11 04:07:34 PM PDT 24	Jun 11 04:17:54 PM PDT 24	3819581496 ps
T897	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1029398868			Jun 11 04:01:32 PM PDT 24	Jun 11 04:04:33 PM PDT 24	2609549560 ps
T898	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4046094100			Jun 11 04:19:30 PM PDT 24	Jun 11 04:38:56 PM PDT 24	5976984400 ps
T899	/workspace/coverage/default/1.chip_sw_aes_enc.1115218491			Jun 11 04:08:53 PM PDT 24	Jun 11 04:12:34 PM PDT 24	3068116458 ps
T900	/workspace/coverage/default/0.chip_sw_example_rom.1129407544			Jun 11 03:57:48 PM PDT 24	Jun 11 03:59:50 PM PDT 24	2311011512 ps
T901	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.724192992			Jun 11 04:17:37 PM PDT 24	Jun 11 04:43:40 PM PDT 24	8932224100 ps
T902	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2430346429			Jun 11 04:23:08 PM PDT 24	Jun 11 04:28:15 PM PDT 24	2874885944 ps
T368	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.4059911360			Jun 11 04:07:00 PM PDT 24	Jun 11 04:10:24 PM PDT 24	2524310140 ps
T322	/workspace/coverage/default/2.chip_sw_otbn_randomness.726686744			Jun 11 04:19:04 PM PDT 24	Jun 11 04:36:24 PM PDT 24	6297675874 ps
T753	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1491981051			Jun 11 04:18:55 PM PDT 24	Jun 11 04:25:53 PM PDT 24	3473298698 ps
T903	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.615366312			Jun 11 04:21:46 PM PDT 24	Jun 11 04:30:50 PM PDT 24	4232425390 ps