Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133974	1			T75	72		T77	5		T79	86
values[2]	8568	1			T79	9		T401	7		T510	1
values[3]	3050	1			T79	1		T470	91		T512	1
values[4]	1886	1			T470	94		T516	8		T564	3
values[5]	1127	1			T470	62		T516	2		T564	14
values[6]	680	1			T470	26		T564	6		T787	35
values[7]	576	1			T470	12		T564	7		T787	14
values[8]	415	1			T470	9		T564	6		T787	15
values[9]	313	1			T564	5		T787	25		T797	1
values[10]	295	1			T564	12		T787	30		T797	1
values[11]	273	1			T564	10		T787	19		T797	1
values[12]	268	1			T564	13		T787	18		T797	1
values[13]	317	1			T564	9		T787	31		T797	1
values[14]	275	1			T564	7		T787	20		T797	1
values[15]	248	1			T564	7		T787	20		T797	1
values[16]	263	1			T564	4		T787	19		T797	1
values[17]	224	1			T564	2		T787	17		T797	1
values[18]	232	1			T564	8		T787	33		T797	1
values[19]	254	1			T564	3		T787	25		T797	1
values[20]	224	1			T564	6		T787	27		T797	1
values[21]	216	1			T564	9		T787	21		T797	1
values[22]	223	1			T564	6		T787	24		T797	1
values[23]	192	1			T564	9		T787	14		T797	1
values[24]	235	1			T564	5		T787	16		T797	1
values[25]	202	1			T564	11		T787	19		T797	1
values[26]	238	1			T564	6		T787	27		T797	1
values[27]	233	1			T564	5		T787	21		T797	1
values[28]	258	1			T564	11		T787	25		T797	1
values[29]	219	1			T564	2		T787	17		T797	1
values[30]	238	1			T564	8		T787	38		T797	1
values[31]	194	1			T564	5		T787	28		T797	1
values[32]	209	1			T564	24		T787	13		T797	1
values[33]	238	1			T564	9		T787	19		T797	1
values[34]	197	1			T564	9		T787	17		T797	1
values[35]	245	1			T564	5		T787	23		T797	1
values[36]	200	1			T564	7		T787	16		T797	1
values[37]	207	1			T564	3		T787	21		T797	1
values[38]	186	1			T564	3		T787	20		T797	1
values[39]	264	1			T564	8		T787	34		T797	1
values[40]	215	1			T564	11		T787	17		T797	1
values[41]	247	1			T564	6		T787	28		T797	1
values[42]	206	1			T564	13		T787	26		T797	1
values[43]	247	1			T564	16		T787	23		T797	1
values[44]	190	1			T564	6		T787	28		T797	1
values[45]	211	1			T564	11		T787	24		T797	1
values[46]	200	1			T564	7		T787	30		T797	1
values[47]	197	1			T564	5		T787	17		T797	1
values[48]	202	1			T564	3		T787	20		T797	1
values[49]	246	1			T564	3		T787	37		T797	1
values[50]	232	1			T564	4		T787	15		T797	1
values[51]	211	1			T564	3		T787	14		T797	1
values[52]	219	1			T564	6		T787	27		T797	1
values[53]	224	1			T564	7		T787	13		T797	1
values[54]	203	1			T564	5		T787	19		T797	1
values[55]	175	1			T564	6		T787	25		T797	1
values[56]	172	1			T564	7		T787	39		T797	1
values[57]	203	1			T564	4		T787	28		T797	1
values[58]	201	1			T564	4		T787	29		T797	1
values[59]	189	1			T564	13		T787	36		T797	1
values[60]	184	1			T564	14		T787	12		T797	1
values[61]	180	1			T564	7		T787	16		T797	1
values[62]	167	1			T564	4		T787	23		T797	1
values[63]	140	1			T564	3		T787	21		T797	1
values[64]	134	1			T787	21		T797	1		T501	15
values[65]	116	1			T787	27		T797	1		T501	2
values[66]	124	1			T787	23		T797	1		T501	7
values[67]	111	1			T787	13		T797	1		T501	9
values[68]	100	1			T787	10		T797	1		T501	14
values[69]	87	1			T787	10		T797	1		T501	7
values[70]	72	1			T787	6		T797	1		T501	7
values[71]	55	1			T787	9		T797	1		T501	2
values[72]	60	1			T787	8		T797	1		T501	6
values[73]	64	1			T787	4		T797	1		T501	2
values[74]	58	1			T787	8		T797	1		T802	1
values[75]	56	1			T787	1		T797	1		T802	1
values[76]	48	1			T797	1		T802	1		T798	2
values[77]	41	1			T797	1		T802	1		T798	2
values[78]	54	1			T797	1		T802	1		T798	2
values[79]	48	1			T797	1		T802	1		T798	2
values[80]	67	1			T797	1		T802	1		T798	2
values[81]	52	1			T797	1		T802	1		T798	2
values[82]	56	1			T797	1		T802	1		T798	2
values[83]	76	1			T797	1		T802	1		T798	2
values[84]	74	1			T797	1		T802	1		T798	2
values[85]	68	1			T797	1		T802	1		T798	2
values[86]	61	1			T797	1		T802	1		T798	2
values[87]	66	1			T797	1		T802	1		T798	2
values[88]	65	1			T797	1		T802	1		T798	2
values[89]	55	1			T797	1		T802	1		T798	2
values[90]	63	1			T797	1		T802	1		T798	2
values[91]	61	1			T797	1		T802	1		T798	2
values[92]	81	1			T797	1		T802	2		T798	2
values[93]	60	1			T797	1		T802	1		T798	2
values[94]	58	1			T797	1		T802	1		T798	2
values[95]	40	1			T797	1		T802	1		T798	2
values[96]	46	1			T797	1		T802	1		T798	2
values[97]	63	1			T797	1		T802	1		T798	2
values[98]	59	1			T797	1		T802	1		T798	2
values[99]	49	1			T797	1		T802	1		T798	2
values[100]	57	1			T797	1		T802	1		T798	3
values[101]	74	1			T797	1		T802	1		T798	2
values[102]	49	1			T797	1		T802	1		T798	2
values[103]	44	1			T797	1		T802	1		T798	2
values[104]	55	1			T797	1		T802	1		T798	2
values[105]	62	1			T797	1		T802	1		T798	2
values[106]	71	1			T797	1		T802	1		T798	2
values[107]	60	1			T797	1		T802	6		T798	2
values[108]	73	1			T797	1		T802	2		T798	2
values[109]	61	1			T797	1		T802	4		T798	2
values[110]	73	1			T797	2		T802	2		T798	2
values[111]	72	1			T797	2		T802	2		T798	2
values[112]	62	1			T797	1		T802	1		T798	2
values[113]	64	1			T797	2		T802	1		T798	2
values[114]	60	1			T797	3		T802	2		T798	2
values[115]	58	1			T797	4		T802	1		T798	2
values[116]	52	1			T797	2		T802	1		T798	2
values[117]	50	1			T797	1		T802	1		T798	3
values[118]	67	1			T797	1		T802	1		T798	4
values[119]	79	1			T797	11		T802	1		T798	4
values[120]	61	1			T797	1		T802	2		T798	2
values[121]	49	1			T797	1		T802	1		T798	2
values[122]	58	1			T797	2		T802	4		T798	3
values[123]	48	1			T797	3		T802	1		T798	3
values[124]	57	1			T797	3		T802	1		T798	2
values[125]	67	1			T797	1		T802	1		T798	3
values[126]	89	1			T797	4		T802	3		T798	4
values[127]	748	1			T797	41		T802	43		T798	69
values[128]	7044	1			T797	270		T802	368		T798	641