Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	471	1			T401	1		T509	1		T674	2
all_values[1]	481	1			T76	2		T401	2		T387	1
all_values[2]	449	1			T401	1		T674	3		T785	1
all_values[3]	441	1			T401	1		T674	1		T516	2
all_values[4]	427	1			T76	1		T401	5		T387	1
all_values[5]	448	1			T401	2		T674	5		T516	4
all_values[6]	422	1			T401	4		T470	1		T785	1
all_values[7]	492	1			T674	3		T516	4		T438	1
all_values[8]	428	1			T401	5		T387	1		T509	1
all_values[9]	442	1			T76	2		T401	3		T387	1
all_values[10]	443	1			T401	2		T387	2		T509	1
all_values[11]	472	1			T401	2		T674	2		T785	1
all_values[12]	463	1			T401	1		T674	3		T516	3
all_values[13]	455	1			T76	1		T387	1		T674	1
all_values[14]	454	1			T76	1		T401	4		T470	1
all_values[15]	434	1			T76	1		T401	1		T387	2
all_values[16]	470	1			T401	1		T674	3		T516	3
all_values[17]	459	1			T401	1		T387	1		T674	1
all_values[18]	434	1			T401	3		T387	1		T674	2
all_values[19]	462	1			T401	1		T674	2		T516	6
all_values[20]	473	1			T76	1		T401	1		T470	2
all_values[21]	463	1			T401	2		T470	1		T674	1
all_values[22]	445	1			T387	2		T509	1		T470	1
all_values[23]	451	1			T401	4		T674	3		T516	1
all_values[24]	465	1			T401	3		T674	2		T516	1
all_values[25]	473	1			T76	1		T401	4		T674	1
all_values[26]	457	1			T401	3		T470	1		T674	1
all_values[27]	444	1			T76	1		T401	2		T674	3
all_values[28]	416	1			T401	1		T387	1		T674	2
all_values[29]	425	1			T401	3		T674	1		T516	3
all_values[30]	461	1			T401	2		T674	5		T516	1
all_values[31]	449	1			T387	1		T516	4		T490	1
all_values[32]	502	1			T401	5		T387	1		T509	2
all_values[33]	409	1			T509	1		T674	1		T516	3
all_values[34]	420	1			T674	5		T516	1		T785	1
all_values[35]	483	1			T401	1		T516	2		T490	1
all_values[36]	496	1			T401	2		T387	1		T509	1
all_values[37]	436	1			T387	1		T470	1		T516	2
all_values[38]	444	1			T76	1		T401	1		T387	3
all_values[39]	451	1			T76	1		T401	1		T470	2
all_values[40]	476	1			T401	2		T509	1		T674	1
all_values[41]	437	1			T76	1		T401	2		T387	2
all_values[42]	449	1			T387	2		T674	4		T450	1
all_values[43]	458	1			T76	1		T401	3		T387	1
all_values[44]	427	1			T76	1		T401	5		T674	4
all_values[45]	478	1			T401	3		T470	1		T674	1
all_values[46]	456	1			T76	1		T401	1		T470	1
all_values[47]	467	1			T401	1		T387	1		T509	1
all_values[48]	467	1			T76	1		T401	1		T387	1
all_values[49]	455	1			T401	2		T387	1		T509	2