Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3462	1			T75	3		T401	26		T387	2
all_values[1]	3480	1			T75	6		T401	31		T387	7
all_values[2]	3429	1			T75	1		T401	32		T387	5
all_values[3]	3396	1			T75	4		T209	1		T401	31
all_values[4]	3436	1			T401	31		T387	4		T510	4
all_values[5]	3314	1			T75	6		T401	26		T387	2
all_values[6]	3492	1			T75	2		T401	32		T387	4
all_values[7]	3439	1			T75	3		T209	1		T401	40
all_values[8]	3442	1			T75	3		T401	22		T387	6
all_values[9]	3542	1			T75	2		T401	19		T387	3
all_values[10]	3377	1			T75	3		T209	1		T401	29
all_values[11]	3474	1			T75	2		T401	31		T387	7
all_values[12]	3560	1			T75	2		T401	29		T387	4
all_values[13]	3459	1			T75	2		T209	1		T401	31
all_values[14]	3445	1			T75	4		T401	30		T387	2
all_values[15]	3415	1			T401	35		T387	3		T510	2
all_values[16]	3434	1			T75	3		T401	39		T387	5
all_values[17]	3483	1			T75	2		T401	29		T387	3
all_values[18]	3448	1			T75	1		T401	38		T387	6
all_values[19]	3454	1			T75	2		T209	1		T401	30
all_values[20]	3510	1			T75	2		T401	29		T387	4
all_values[21]	3558	1			T75	4		T401	31		T387	3
all_values[22]	3408	1			T75	1		T209	1		T401	39
all_values[23]	3497	1			T75	3		T401	37		T387	2
all_values[24]	3593	1			T75	2		T401	30		T387	3
all_values[25]	3339	1			T75	4		T401	19		T387	7
all_values[26]	3460	1			T75	2		T401	24		T387	3
all_values[27]	3458	1			T75	5		T401	27		T387	7
all_values[28]	3487	1			T401	32		T387	6		T510	2
all_values[29]	3473	1			T75	1		T401	24		T387	5
all_values[30]	3363	1			T75	1		T401	29		T387	3
all_values[31]	3554	1			T75	1		T401	35		T387	2
all_values[32]	3457	1			T75	2		T401	42		T387	7
all_values[33]	3423	1			T75	1		T401	32		T387	1
all_values[34]	3465	1			T75	6		T401	20		T387	3
all_values[35]	3420	1			T75	5		T401	33		T387	6
all_values[36]	3502	1			T75	1		T401	44		T387	2
all_values[37]	3358	1			T75	1		T401	26		T387	3
all_values[38]	3545	1			T75	2		T401	34		T387	6
all_values[39]	3523	1			T75	1		T401	15		T387	4
all_values[40]	3527	1			T75	1		T401	29		T387	2
all_values[41]	3435	1			T75	3		T209	1		T401	27
all_values[42]	3468	1			T401	17		T387	7		T510	1
all_values[43]	3528	1			T75	3		T401	24		T387	2
all_values[44]	3473	1			T75	2		T209	1		T401	19
all_values[45]	3468	1			T75	2		T401	29		T387	4
all_values[46]	3332	1			T75	3		T401	23		T387	7
all_values[47]	3541	1			T75	5		T401	37		T387	5
all_values[48]	3348	1			T75	3		T401	26		T387	5
all_values[49]	3450	1			T75	2		T401	23		T387	6
all_values[50]	3368	1			T75	2		T401	29		T387	4
all_values[51]	3489	1			T75	5		T401	31		T387	6
all_values[52]	3382	1			T75	1		T401	28		T387	2
all_values[53]	3456	1			T75	2		T401	26		T387	7
all_values[54]	3414	1			T75	2		T401	22		T387	5
all_values[55]	3389	1			T75	1		T401	25		T387	1
all_values[56]	3463	1			T401	30		T387	3		T510	1
all_values[57]	3415	1			T75	1		T401	34		T387	8
all_values[58]	3526	1			T401	25		T387	5		T510	2
all_values[59]	3510	1			T75	2		T401	22		T387	7
all_values[60]	3441	1			T75	1		T401	24		T510	1
all_values[61]	3534	1			T75	3		T401	31		T387	4
all_values[62]	3501	1			T75	4		T209	1		T401	27
all_values[63]	3364	1			T209	1		T401	18		T387	2