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LINE 36651
EXPRESSION (addr_hit[552] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T401,T429,T494 |
| 1 | 1 | 1 | Covered | T8,T9,T381 |
LINE 36653
EXPRESSION (addr_hit[553] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T429,T528,T520 |
| 1 | 1 | 1 | Covered | T117,T360,T365 |
LINE 36655
EXPRESSION (addr_hit[554] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T520,T521,T523 |
| 1 | 1 | 1 | Covered | T117,T360,T365 |
LINE 36657
EXPRESSION (addr_hit[555] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T535,T521,T525 |
| 1 | 1 | 1 | Covered | T117,T360,T365 |
LINE 36659
EXPRESSION (addr_hit[556] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T429,T528,T520 |
| 1 | 1 | 1 | Covered | T117,T387,T360 |
LINE 36661
EXPRESSION (addr_hit[557] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T521,T523,T533 |
| 1 | 1 | 1 | Covered | T117,T360,T365 |
LINE 36663
EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T520,T487,T521 |
| 1 | 1 | 1 | Covered | T117,T409,T360 |
LINE 36665
EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T520,T521,T523 |
| 1 | 1 | 1 | Covered | T7,T12,T13 |
LINE 36668
EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T429,T528,T431 |
| 1 | 1 | 1 | Covered | T15,T76,T117 |
LINE 36671
EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T76,T524,T541 |
| 1 | 1 | 1 | Covered | T117,T387,T360 |
LINE 36674
EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T520,T521,T523 |
| 1 | 1 | 1 | Covered | T11,T117,T360 |
LINE 36677
EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T530,T521,T523 |
| 1 | 1 | 1 | Covered | T117,T387,T360 |
LINE 36680
EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T429,T520,T524 |
| 1 | 1 | 1 | Covered | T1,T3,T10 |
LINE 36683
EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T76,T438,T605 |
| 1 | 1 | 1 | Covered | T117,T360,T365 |
LINE 36686
EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T520,T525,T618 |
| 1 | 1 | 1 | Covered | T2,T117,T401 |
LINE 36689
EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T490,T520,T501 |
| 1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 40162
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |