Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	505	1			T75	1		T79	5		T249	1
all_values[1]	497	1			T74	1		T79	5		T249	1
all_values[2]	492	1			T78	1		T79	3		T239	4
all_values[3]	534	1			T75	1		T79	5		T239	2
all_values[4]	542	1			T79	5		T239	3		T558	1
all_values[5]	472	1			T79	2		T249	1		T239	3
all_values[6]	506	1			T78	1		T79	2		T249	1
all_values[7]	462	1			T74	2		T249	1		T239	2
all_values[8]	449	1			T74	1		T78	1		T79	3
all_values[9]	495	1			T75	1		T79	1		T249	1
all_values[10]	480	1			T79	2		T239	2		T558	1
all_values[11]	496	1			T78	1		T79	1		T239	4
all_values[12]	491	1			T79	2		T239	1		T451	1
all_values[13]	505	1			T75	1		T249	1		T239	1
all_values[14]	487	1			T79	5		T239	5		T475	2
all_values[15]	529	1			T74	1		T79	3		T239	1
all_values[16]	548	1			T75	1		T79	3		T239	1
all_values[17]	491	1			T75	2		T79	2		T239	4
all_values[18]	493	1			T249	1		T239	1		T475	3
all_values[19]	502	1			T79	1		T249	1		T239	2
all_values[20]	502	1			T79	2		T239	3		T475	4
all_values[21]	483	1			T74	1		T79	3		T239	2
all_values[22]	493	1			T74	1		T79	2		T249	1
all_values[23]	510	1			T79	2		T249	2		T239	2
all_values[24]	477	1			T75	1		T79	4		T239	4
all_values[25]	460	1			T79	3		T239	4		T475	2
all_values[26]	474	1			T79	3		T239	1		T475	5
all_values[27]	516	1			T75	1		T79	5		T249	1
all_values[28]	515	1			T75	1		T79	5		T239	3
all_values[29]	492	1			T79	1		T239	1		T475	4
all_values[30]	500	1			T75	1		T79	5		T249	1
all_values[31]	494	1			T79	3		T249	1		T239	1
all_values[32]	511	1			T79	3		T239	2		T475	2
all_values[33]	506	1			T79	6		T249	1		T239	1
all_values[34]	525	1			T79	2		T239	2		T475	4
all_values[35]	484	1			T79	1		T451	1		T475	2
all_values[36]	482	1			T78	1		T79	1		T249	2
all_values[37]	485	1			T74	1		T79	3		T249	1
all_values[38]	504	1			T79	4		T249	1		T239	3
all_values[39]	505	1			T78	2		T79	6		T239	4
all_values[40]	517	1			T75	1		T79	6		T249	1
all_values[41]	496	1			T74	2		T79	1		T249	1
all_values[42]	505	1			T79	3		T249	3		T239	2
all_values[43]	503	1			T79	2		T249	2		T239	1
all_values[44]	465	1			T75	1		T78	1		T79	3
all_values[45]	519	1			T74	1		T78	1		T79	4
all_values[46]	498	1			T79	2		T249	1		T239	2
all_values[47]	497	1			T79	1		T239	1		T475	5
all_values[48]	511	1			T78	1		T79	3		T239	3
all_values[49]	459	1			T78	1		T79	2		T249	1