Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.49	93.94	95.40		94.74	97.53	99.51

Total tests in report: 2873

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.44	39.44	44.64	44.64	42.92	42.92	31.44	31.44			57.83	57.83	59.44	59.44	0.39	0.39	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2042691776
48.71	9.26	52.17	7.53	51.83	8.90	36.54	5.10			65.65	7.82	85.31	25.87	0.73	0.34	/workspace/coverage/default/1.chip_jtag_csr_rw.789542222
54.12	5.41	60.64	8.47	57.68	5.86	41.36	4.81			66.56	0.91	85.31	0.00	13.16	12.43	/workspace/coverage/cover_reg_top/91.xbar_stress_all.35654394
59.52	5.40	72.48	11.84	65.67	7.99	43.26	1.91			77.25	10.69	85.31	0.00	13.16	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.4103092126
63.41	3.89	72.48	0.00	65.67	0.00	43.26	0.00			77.25	0.00	85.31	0.00	36.47	23.31	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3677028670
66.80	3.39	72.48	0.00	65.67	0.00	43.26	0.00			77.25	0.00	85.31	0.00	56.83	20.36	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.4285245197
70.17	3.37	78.35	5.87	69.81	4.14	47.20	3.94			79.16	1.92	89.69	4.37	56.83	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.565962896
72.80	2.62	78.36	0.01	69.83	0.02	62.90	15.70			79.18	0.02	89.69	0.00	56.83	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3410657212
75.21	2.41	81.14	2.78	76.22	6.39	63.08	0.18			83.51	4.33	89.69	0.00	57.63	0.80	/workspace/coverage/cover_reg_top/12.chip_csr_rw.880309301
77.48	2.27	84.55	3.42	78.90	2.68	68.39	5.31			85.39	1.87	89.86	0.17	57.77	0.14	/workspace/coverage/default/2.chip_jtag_csr_rw.1704830233
79.10	1.62	84.55	0.00	79.20	0.30	68.39	0.00			85.42	0.03	89.86	0.00	67.16	9.39	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3018596609
80.64	1.54	84.56	0.01	79.44	0.24	69.13	0.74			85.45	0.03	89.86	0.00	75.40	8.24	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1378765821
82.12	1.48	84.64	0.08	79.46	0.01	77.72	8.59			85.46	0.01	90.03	0.17	75.40	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1966377345
83.21	1.10	84.64	0.00	79.46	0.00	77.72	0.00			85.46	0.00	90.03	0.00	81.98	6.58	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1954918747
84.30	1.09	84.97	0.33	80.25	0.79	80.53	2.81			85.95	0.50	90.21	0.17	83.90	1.93	/workspace/coverage/default/2.chip_sw_alert_test.2105578221
85.24	0.94	86.78	1.81	81.77	1.52	81.62	1.08			87.19	1.23	90.21	0.00	83.90	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.657321940
86.05	0.81	86.78	0.00	81.77	0.00	81.62	0.00			87.19	0.00	90.21	0.00	88.76	4.85	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.773563808
86.82	0.77	87.21	0.43	81.93	0.17	81.63	0.01			87.36	0.17	94.06	3.85	88.76	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2605572077
87.51	0.69	88.26	1.05	82.79	0.85	81.94	0.31			88.40	1.04	94.93	0.87	88.76	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3733904005
88.18	0.67	89.05	0.78	84.31	1.52	82.02	0.08			90.04	1.65	94.93	0.00	88.76	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1985152253
88.81	0.63	89.05	0.00	84.40	0.09	82.02	0.00			90.04	0.00	94.93	0.00	92.45	3.69	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3015533696
89.41	0.60	89.05	0.00	84.40	0.00	85.61	3.59			90.04	0.00	94.93	0.00	92.45	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1729259131
89.97	0.55	90.13	1.09	85.31	0.91	85.84	0.23			91.14	1.10	94.93	0.00	92.45	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.746145849
90.50	0.53	90.13	0.00	85.42	0.11	85.84	0.00			91.14	0.00	94.93	0.00	95.54	3.09	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4015032794
91.03	0.53	90.84	0.71	85.97	0.55	87.05	1.20			91.70	0.56	95.10	0.17	95.54	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3407058436
91.54	0.51	91.88	1.04	86.26	0.29	87.73	0.69			91.85	0.15	95.98	0.87	95.54	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3541975179
92.00	0.46	91.89	0.01	88.61	2.35	87.73	0.00			91.85	0.00	95.98	0.00	95.95	0.41	/workspace/coverage/cover_reg_top/14.chip_tl_errors.3352348799
92.44	0.44	92.70	0.80	89.18	0.57	88.10	0.36			92.74	0.88	95.98	0.00	95.95	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3580370725
92.75	0.31	93.20	0.50	89.61	0.43	88.59	0.49			93.18	0.44	95.98	0.00	95.95	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3388755525
92.94	0.19	93.21	0.01	89.62	0.01	89.73	1.14			93.18	0.00	95.98	0.00	95.95	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2124656198
93.13	0.19	93.51	0.30	90.25	0.63	89.76	0.03			93.35	0.17	95.98	0.00	95.95	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3515142258
93.32	0.19	93.51	0.00	90.25	0.00	89.76	0.00			93.35	0.00	95.98	0.00	97.07	1.13	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3491030004
93.48	0.16	93.72	0.21	90.41	0.16	89.85	0.09			93.52	0.17	96.33	0.35	97.07	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3250183192
93.63	0.15	93.93	0.21	90.73	0.32	90.21	0.36			93.52	0.00	96.33	0.00	97.07	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4206896275
93.78	0.15	93.93	0.00	90.73	0.00	91.09	0.88			93.52	0.00	96.33	0.00	97.07	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3702716973
93.90	0.12	93.98	0.06	91.03	0.30	91.14	0.05			93.84	0.32	96.33	0.00	97.07	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3972517290
94.02	0.12	93.98	0.00	91.03	0.00	91.80	0.66			93.84	0.00	96.33	0.00	97.11	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3939187153
94.13	0.11	93.98	0.00	91.04	0.01	91.80	0.00			93.84	0.00	96.33	0.00	97.77	0.66	/workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.180380988
94.24	0.11	93.99	0.01	91.04	0.01	92.45	0.64			93.84	0.00	96.33	0.00	97.77	0.00	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2734018059
94.34	0.10	94.02	0.03	91.13	0.09	92.71	0.26			93.90	0.06	96.50	0.17	97.77	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3168269080
94.42	0.08	94.02	0.00	91.13	0.00	93.17	0.47			93.90	0.00	96.50	0.00	97.77	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3470199062
94.48	0.06	94.09	0.07	91.19	0.06	93.19	0.01			93.96	0.06	96.68	0.17	97.78	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3728463949
94.54	0.06	94.09	0.00	91.57	0.38	93.19	0.00			93.96	0.00	96.68	0.00	97.78	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1596419311
94.61	0.06	94.09	0.00	91.57	0.00	93.56	0.38			93.96	0.00	96.68	0.00	97.78	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1330378884
94.66	0.06	94.09	0.00	91.73	0.16	93.56	0.00			94.14	0.18	96.68	0.00	97.78	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3345184988
94.72	0.05	94.09	0.00	91.73	0.00	93.56	0.00			94.14	0.00	96.68	0.00	98.11	0.33	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2852211874
94.77	0.05	94.09	0.00	91.76	0.04	93.56	0.00			94.14	0.00	96.68	0.00	98.37	0.26	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3875767352
94.81	0.05	94.15	0.07	91.87	0.11	93.57	0.01			94.24	0.10	96.68	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3249596711
94.86	0.04	94.22	0.07	91.93	0.06	93.68	0.12			94.25	0.02	96.68	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/84.xbar_stress_all.3036550850
94.90	0.04	94.28	0.07	92.06	0.12	93.68	0.00			94.32	0.06	96.68	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1029796116
94.94	0.04	94.28	0.00	92.06	0.00	93.93	0.24			94.32	0.00	96.68	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.816832576
94.98	0.04	94.30	0.01	92.07	0.01	93.93	0.00			94.34	0.02	96.85	0.17	98.38	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872506592
95.02	0.04	94.32	0.03	92.08	0.01	93.93	0.01			94.35	0.01	97.03	0.17	98.39	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3324134246
95.05	0.04	94.32	0.00	92.08	0.00	94.16	0.23			94.35	0.00	97.03	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3492794501
95.09	0.04	94.33	0.01	92.09	0.01	94.16	0.01			94.36	0.01	97.20	0.17	98.40	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2561848163
95.13	0.04	94.33	0.01	92.10	0.01	94.16	0.00			94.37	0.01	97.38	0.17	98.41	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028252921
95.16	0.03	94.33	0.00	92.10	0.00	94.19	0.03			94.37	0.00	97.55	0.17	98.41	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1735721228
95.19	0.03	94.33	0.00	92.23	0.13	94.19	0.00			94.43	0.06	97.55	0.00	98.41	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3426423101
95.22	0.03	94.33	0.00	92.42	0.19	94.19	0.00			94.43	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.799223853
95.25	0.03	94.37	0.04	92.49	0.07	94.23	0.04			94.47	0.04	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3750469287
95.29	0.03	94.40	0.03	92.52	0.03	94.32	0.09			94.49	0.02	97.55	0.00	98.43	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2505687031
95.31	0.03	94.40	0.00	92.69	0.17	94.32	0.00			94.49	0.00	97.55	0.00	98.44	0.01	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2502453055
95.34	0.03	94.47	0.07	92.69	0.00	94.41	0.09			94.50	0.01	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2664013313
95.37	0.03	94.47	0.00	92.69	0.00	94.58	0.17			94.50	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1936313434
95.40	0.03	94.54	0.07	92.72	0.03	94.59	0.01			94.55	0.05	97.55	0.00	98.44	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2627073638
95.42	0.02	94.61	0.07	92.77	0.05	94.59	0.00			94.58	0.03	97.55	0.00	98.44	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3765038908
95.45	0.02	94.61	0.00	92.81	0.04	94.59	0.00			94.58	0.00	97.55	0.00	98.53	0.09	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2634188267
95.47	0.02	94.66	0.06	92.86	0.05	94.59	0.00			94.60	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.866853844
95.49	0.02	94.67	0.01	92.88	0.02	94.69	0.09			94.61	0.01	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.32264847
95.51	0.02	94.67	0.00	92.92	0.04	94.73	0.04			94.64	0.02	97.55	0.00	98.54	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2423687689
95.53	0.02	94.67	0.00	93.04	0.12	94.73	0.00			94.64	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1957017252
95.55	0.02	94.70	0.03	93.08	0.05	94.74	0.01			94.66	0.02	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1301461402
95.56	0.02	94.70	0.00	93.17	0.08	94.74	0.00			94.68	0.02	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/90.xbar_stress_all.3867686079
95.58	0.02	94.72	0.02	93.24	0.07	94.75	0.01			94.68	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.148571607
95.60	0.02	94.72	0.00	93.33	0.10	94.75	0.00			94.68	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1352505910
95.61	0.02	94.72	0.00	93.36	0.03	94.75	0.00			94.69	0.02	97.55	0.00	98.59	0.05	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3997462290
95.62	0.01	94.72	0.00	93.36	0.00	94.83	0.08			94.69	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.993537222
95.64	0.01	94.72	0.00	93.36	0.00	94.91	0.08			94.69	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3850551180
95.65	0.01	94.72	0.00	93.37	0.01	94.91	0.00			94.69	0.00	97.55	0.00	98.66	0.07	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3726809807
95.67	0.01	94.72	0.00	93.45	0.08	94.91	0.00			94.69	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.978934115
95.68	0.01	94.74	0.02	93.47	0.02	94.94	0.03			94.69	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2106096256
95.69	0.01	94.77	0.03	93.48	0.01	94.98	0.04			94.69	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1685678077
95.70	0.01	94.81	0.03	93.50	0.02	94.98	0.00			94.70	0.01	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3284520848
95.71	0.01	94.83	0.02	93.51	0.01	94.99	0.01			94.72	0.02	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4089051025
95.72	0.01	94.83	0.00	93.51	0.00	95.04	0.05			94.72	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2699419001
95.73	0.01	94.84	0.01	93.51	0.00	95.08	0.04			94.72	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1946971624
95.73	0.01	94.84	0.00	93.51	0.00	95.12	0.05			94.72	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3616851744
95.74	0.01	94.84	0.00	93.55	0.05	95.12	0.00			94.72	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.3664277223
95.75	0.01	94.84	0.00	93.55	0.01	95.12	0.00			94.72	0.00	97.55	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.604497666
95.75	0.01	94.85	0.01	93.56	0.01	95.14	0.01			94.73	0.01	97.55	0.00	98.70	0.00	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1584703531
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95.97	0.01	94.89	0.00	93.81	0.00	95.33	0.00			94.73	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2951419522
95.97	0.01	94.89	0.00	93.81	0.00	95.33	0.00			94.73	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1145098486
95.97	0.01	94.89	0.00	93.82	0.01	95.33	0.00			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.437608720
95.97	0.01	94.89	0.00	93.83	0.01	95.33	0.00			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.4044838247
95.98	0.01	94.89	0.00	93.84	0.01	95.33	0.00			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2940800380
95.98	0.01	94.89	0.00	93.85	0.01	95.33	0.00			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3127626193
95.98	0.01	94.90	0.01	93.86	0.01	95.33	0.00			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3968765800
95.98	0.01	94.90	0.01	93.86	0.00	95.33	0.01			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1328522981
95.98	0.01	94.90	0.00	93.86	0.00	95.34	0.01			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2322963819
95.98	0.01	94.90	0.00	93.86	0.00	95.35	0.01			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4098594339
95.99	0.01	94.90	0.00	93.86	0.01	95.36	0.01			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1125263895
95.99	0.01	94.90	0.00	93.87	0.01	95.36	0.01			94.73	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3988111371
95.99	0.01	94.90	0.00	93.87	0.00	95.36	0.00			94.74	0.01	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.705282389
95.99	0.01	94.90	0.00	93.87	0.01	95.36	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all.1305647611
95.99	0.01	94.90	0.00	93.88	0.01	95.36	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3001130193
95.99	0.01	94.91	0.01	93.88	0.01	95.36	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.561526772
95.99	0.01	94.91	0.00	93.89	0.01	95.36	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_aon_timer_irq.939252630
95.99	0.01	94.91	0.00	93.89	0.00	95.37	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3432042251
95.99	0.01	94.91	0.00	93.89	0.00	95.37	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3603522558
95.99	0.01	94.91	0.00	93.89	0.00	95.38	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.427878150
96.00	0.01	94.91	0.00	93.89	0.00	95.38	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3060029109
96.00	0.01	94.91	0.00	93.89	0.00	95.39	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.394664167
96.00	0.01	94.91	0.00	93.89	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2032713932
96.00	0.01	94.91	0.00	93.89	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.173407662
96.00	0.01	94.91	0.00	93.90	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.4274969403
96.00	0.01	94.91	0.00	93.90	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3238153078
96.00	0.01	94.91	0.00	93.90	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3873774988
96.00	0.01	94.91	0.00	93.91	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.4182754365
96.00	0.01	94.91	0.00	93.91	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2004585085
96.00	0.01	94.91	0.00	93.92	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2069526895
96.00	0.01	94.91	0.00	93.92	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3082003722
96.00	0.01	94.91	0.00	93.92	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.4284660315
96.00	0.01	94.91	0.00	93.93	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2185010323
96.00	0.01	94.91	0.00	93.93	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4183018663
96.00	0.01	94.91	0.00	93.93	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.461789772
96.00	0.01	94.91	0.00	93.94	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3612874317
96.01	0.01	94.91	0.00	93.94	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2469934078
96.01	0.01	94.91	0.00	93.94	0.01	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2538805776
96.01	0.01	94.91	0.01	93.94	0.00	95.39	0.00			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3679401439
96.01	0.01	94.91	0.00	93.94	0.00	95.39	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2082230688
96.01	0.01	94.91	0.00	93.94	0.00	95.39	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1053955709
96.01	0.01	94.91	0.00	93.94	0.00	95.39	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.467591122
96.01	0.01	94.91	0.00	93.94	0.00	95.40	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.201720177
96.01	0.01	94.91	0.00	93.94	0.00	95.40	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1372552549
96.01	0.01	94.91	0.00	93.94	0.00	95.40	0.01			94.74	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4146417734

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3506839765
/workspace/coverage/cover_reg_top/0.chip_csr_rw.904231427
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3662576399
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2994429175
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3345652226
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.546120255
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3243346719
/workspace/coverage/cover_reg_top/0.xbar_error_random.1058844008
/workspace/coverage/cover_reg_top/0.xbar_random.3432396985
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1414354153
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3556584455
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.816533504
/workspace/coverage/cover_reg_top/0.xbar_same_source.245006414
/workspace/coverage/cover_reg_top/0.xbar_smoke.368074528
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2135984394
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.72190276
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3646782308
/workspace/coverage/cover_reg_top/0.xbar_stress_all.418244688
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.986243074
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3335693673
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2783762346
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2507915232
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3117370208
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1848434005
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3872960792
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2573537241
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2501899843
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4128239566
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1781865628
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3884063574
/workspace/coverage/cover_reg_top/1.xbar_error_random.1608819786
/workspace/coverage/cover_reg_top/1.xbar_random.2008790531
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1999031377
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3678947553
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3284217335
/workspace/coverage/cover_reg_top/1.xbar_same_source.3248971481
/workspace/coverage/cover_reg_top/1.xbar_smoke.2646796654
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1745255938
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.743676761
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.983334994
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2967172447
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2440464790
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3570924517
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3856741843
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1332357608
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.633222188
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1193409585
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4143432788
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1616605572
/workspace/coverage/cover_reg_top/10.xbar_error_random.1553793667
/workspace/coverage/cover_reg_top/10.xbar_random.3490466399
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.4098778529
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3484513712
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.827385716
/workspace/coverage/cover_reg_top/10.xbar_same_source.1118018798
/workspace/coverage/cover_reg_top/10.xbar_smoke.4031388459
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3240505841
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1424454412
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3775163968
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1749197234
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3896524040
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.859930318
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1950951703
/workspace/coverage/cover_reg_top/11.chip_csr_rw.856089295
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1403283682
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2924217160
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3884594867
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.208682731
/workspace/coverage/cover_reg_top/11.xbar_error_random.2447647438
/workspace/coverage/cover_reg_top/11.xbar_random.2233263037
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3195457672
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1965753777
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2311266574
/workspace/coverage/cover_reg_top/11.xbar_same_source.659335656
/workspace/coverage/cover_reg_top/11.xbar_smoke.3956645176
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1205044205
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.127175621
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.670109445
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4149636648
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3769895112
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.965989438
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3077431600
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3085022773
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3640995915
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.4183139712
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3961669918
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4235695736
/workspace/coverage/cover_reg_top/12.xbar_error_random.1527919064
/workspace/coverage/cover_reg_top/12.xbar_random.2922460404
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3281704079
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1751239720
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1156521143
/workspace/coverage/cover_reg_top/12.xbar_same_source.871035502
/workspace/coverage/cover_reg_top/12.xbar_smoke.938727151
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4279474013
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3693895255
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3375403825
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1189888977
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3048583005
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3082983582
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4292706733
/workspace/coverage/cover_reg_top/13.chip_csr_rw.312421709
/workspace/coverage/cover_reg_top/13.chip_tl_errors.844296736
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1709676400
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3836958896
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2609531794
/workspace/coverage/cover_reg_top/13.xbar_error_random.2222495514
/workspace/coverage/cover_reg_top/13.xbar_random.3415210367
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2093526664
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1077033817
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1362076946
/workspace/coverage/cover_reg_top/13.xbar_same_source.1093884229
/workspace/coverage/cover_reg_top/13.xbar_smoke.3553194811
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3204021083
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1756983733
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1927981360
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3843809370
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1183423825
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.776256526
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.627085578
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2051343642
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1062917554
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3781679017
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2325119876
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3143030655
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3689657903
/workspace/coverage/cover_reg_top/14.xbar_error_random.1182374763
/workspace/coverage/cover_reg_top/14.xbar_random.2472245381
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.4211414709
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3872117788
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2020189110
/workspace/coverage/cover_reg_top/14.xbar_same_source.974508509
/workspace/coverage/cover_reg_top/14.xbar_smoke.3277871436
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3508813657
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1863662854
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/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3665895506
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4277728611
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2787035020
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2931762692
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1110569972
/workspace/coverage/default/3.chip_sw_uart_tx_rx.2619581822
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.942528494
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1101585617
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1600356326
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2213203379
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4077283555
/workspace/coverage/default/3.chip_tap_straps_dev.1736914265
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/workspace/coverage/default/3.chip_tap_straps_rma.662850341
/workspace/coverage/default/3.chip_tap_straps_testunlock0.2763554365
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3596537354
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2892711679
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1849909776
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596929018
/workspace/coverage/default/34.chip_sw_all_escalation_resets.43099305
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1913508216
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1777741540
/workspace/coverage/default/38.chip_sw_all_escalation_resets.972409453
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.181641201
/workspace/coverage/default/39.chip_sw_all_escalation_resets.187328596
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.161690673
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3470173278
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1218128420
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1636054692
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3792233537
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1380554801
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2650719787
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3113299485
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.12105872
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3759082829
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3473145150
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1273761521
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3742485504
/workspace/coverage/default/4.chip_tap_straps_dev.244924851
/workspace/coverage/default/4.chip_tap_straps_prod.19828749
/workspace/coverage/default/4.chip_tap_straps_rma.30599185
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2126041101
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3269713140
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836922216
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520500079
/workspace/coverage/default/42.chip_sw_all_escalation_resets.373240884
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172137283
/workspace/coverage/default/43.chip_sw_all_escalation_resets.644965065
/workspace/coverage/default/44.chip_sw_all_escalation_resets.526876305
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882090202
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2479709753
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2721613080
/workspace/coverage/default/48.chip_sw_all_escalation_resets.798603146
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155811418
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2041016349
/workspace/coverage/default/5.chip_sw_all_escalation_resets.345782869
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.610257076
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4290858416
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2861765079
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.947169261
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.409863256
/workspace/coverage/default/50.chip_sw_all_escalation_resets.392442150
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1901911784
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1276757729
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3986869554
/workspace/coverage/default/53.chip_sw_all_escalation_resets.294695903
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410282723
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1231355712
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.343377003
/workspace/coverage/default/57.chip_sw_all_escalation_resets.609447908
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2213121893
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2685803048
/workspace/coverage/default/59.chip_sw_all_escalation_resets.41312536
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3399497621
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3210859863
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.122133788
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1252535644
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3711231798
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366709540
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2148742812
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2074362638
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2684872644
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084445991
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2826732828
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1592746873
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2730011582
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2957972927
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.315481633
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2067638193
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2528759131
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2149157438
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1116938820
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2708100423
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1184642851
/workspace/coverage/default/69.chip_sw_all_escalation_resets.691141993
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709205179
/workspace/coverage/default/7.chip_sw_all_escalation_resets.302259980
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4280391616
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.576251313
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1091321872
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3886343610
/workspace/coverage/default/70.chip_sw_all_escalation_resets.208807714
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050434729
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1893344730
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029236979
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1869862283
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461419369
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2753723746
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1361603571
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3465426604
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810077640
/workspace/coverage/default/77.chip_sw_all_escalation_resets.221196309
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2571011839
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1999306155
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.133713240
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3115844171
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1352567952
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3792971510
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1657330507
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2068787978
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1425318229
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649136707
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2693524907
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1379621784
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1580990103
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3893689443
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2848051211
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172400737
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2573649462
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1486025679
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2295089620
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688235485
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3240004368
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2648971420
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2881860962
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3203094371
/workspace/coverage/default/89.chip_sw_all_escalation_resets.4172659240
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.250701814
/workspace/coverage/default/9.chip_sw_all_escalation_resets.418968383
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4102933959
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.299486892
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1292705538
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1943512881
/workspace/coverage/default/91.chip_sw_all_escalation_resets.810886380
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2422133340
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3950235677
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3917191967
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3134262921
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2504869791
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3096668457
/workspace/coverage/default/99.chip_sw_all_escalation_resets.797486725
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.4084240973
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1435050759
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2807643226
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3134433930
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1320073744
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3287075278
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.120051982
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3328662689

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Total test records in report: 2873

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1066552270			Jun 21 08:14:26 PM PDT 24	Jun 21 08:19:06 PM PDT 24	2711448548 ps
T5	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2423687689			Jun 21 07:59:25 PM PDT 24	Jun 21 08:09:00 PM PDT 24	7199388600 ps
T6	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2042691776			Jun 21 08:36:23 PM PDT 24	Jun 21 08:43:26 PM PDT 24	4919636776 ps
T18	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2573649462			Jun 21 08:34:54 PM PDT 24	Jun 21 08:44:51 PM PDT 24	5748082684 ps
T51	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3470199062			Jun 21 08:06:49 PM PDT 24	Jun 21 09:08:02 PM PDT 24	14758998360 ps
T85	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3410657212			Jun 21 08:00:17 PM PDT 24	Jun 21 08:22:43 PM PDT 24	7780021663 ps
T86	/workspace/coverage/default/0.chip_sw_kmac_idle.2746100893			Jun 21 07:59:54 PM PDT 24	Jun 21 08:04:59 PM PDT 24	2665902860 ps
T87	/workspace/coverage/default/2.chip_sw_otbn_smoketest.979523108			Jun 21 08:24:05 PM PDT 24	Jun 21 08:42:43 PM PDT 24	5690069668 ps
T88	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.6823985			Jun 21 08:20:51 PM PDT 24	Jun 21 08:29:18 PM PDT 24	3444438894 ps
T89	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2401850819			Jun 21 08:03:25 PM PDT 24	Jun 21 08:18:21 PM PDT 24	5303637856 ps
T113	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3580370725			Jun 21 08:15:04 PM PDT 24	Jun 21 08:50:02 PM PDT 24	8491312532 ps
T61	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3505168763			Jun 21 08:02:55 PM PDT 24	Jun 21 08:27:35 PM PDT 24	9228646548 ps
T110	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2168669413			Jun 21 08:04:43 PM PDT 24	Jun 21 08:26:38 PM PDT 24	5661230844 ps
T63	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2505687031			Jun 21 08:34:27 PM PDT 24	Jun 21 08:46:11 PM PDT 24	6174565824 ps
T714	/workspace/coverage/default/0.chip_sw_hmac_oneshot.1769336795			Jun 21 07:59:39 PM PDT 24	Jun 21 08:07:17 PM PDT 24	3315079638 ps
T27	/workspace/coverage/default/1.chip_sw_gpio_smoketest.657321940			Jun 21 08:13:30 PM PDT 24	Jun 21 08:18:34 PM PDT 24	3674743784 ps
T111	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3057845092			Jun 21 08:01:55 PM PDT 24	Jun 21 08:15:49 PM PDT 24	4854165194 ps
T894	/workspace/coverage/default/0.chip_sw_example_manufacturer.2848943028			Jun 21 07:58:29 PM PDT 24	Jun 21 08:02:45 PM PDT 24	2880531200 ps
T165	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1379790951			Jun 21 08:20:28 PM PDT 24	Jun 21 08:29:19 PM PDT 24	4734462520 ps
T19	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3507536476			Jun 21 08:00:36 PM PDT 24	Jun 21 08:10:57 PM PDT 24	9381665762 ps
T182	/workspace/coverage/default/5.chip_sw_all_escalation_resets.345782869			Jun 21 08:27:38 PM PDT 24	Jun 21 08:37:11 PM PDT 24	5691692082 ps
T20	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.299486892			Jun 21 08:26:51 PM PDT 24	Jun 21 08:41:20 PM PDT 24	11233939463 ps
T252	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1151466048			Jun 21 08:17:39 PM PDT 24	Jun 21 08:23:07 PM PDT 24	3787277782 ps
T54	/workspace/coverage/default/2.chip_jtag_csr_rw.1704830233			Jun 21 08:13:33 PM PDT 24	Jun 21 08:38:50 PM PDT 24	12563534492 ps
T308	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2976779308			Jun 21 08:29:36 PM PDT 24	Jun 21 08:35:18 PM PDT 24	3974804232 ps
T55	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2955319069			Jun 21 07:58:38 PM PDT 24	Jun 21 08:39:13 PM PDT 24	23551390922 ps
T247	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3474610166			Jun 21 08:05:59 PM PDT 24	Jun 21 08:14:42 PM PDT 24	4032663544 ps
T331	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1366237360			Jun 21 08:19:53 PM PDT 24	Jun 21 08:26:54 PM PDT 24	3693842966 ps
T57	/workspace/coverage/default/2.chip_sw_alert_test.2105578221			Jun 21 08:19:03 PM PDT 24	Jun 21 08:26:11 PM PDT 24	2707738832 ps
T149	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.198055287			Jun 21 08:16:04 PM PDT 24	Jun 21 08:48:45 PM PDT 24	10388986792 ps
T306	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810077640			Jun 21 08:34:17 PM PDT 24	Jun 21 08:40:41 PM PDT 24	3754385262 ps
T173	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3918764438			Jun 21 08:05:24 PM PDT 24	Jun 21 08:15:02 PM PDT 24	3210457000 ps
T284	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1657330507			Jun 21 08:34:55 PM PDT 24	Jun 21 08:45:13 PM PDT 24	6015468996 ps
T159	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2734018059			Jun 21 08:31:59 PM PDT 24	Jun 21 08:42:28 PM PDT 24	4835111680 ps
T285	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.121313607			Jun 21 08:18:13 PM PDT 24	Jun 21 08:22:38 PM PDT 24	2955023306 ps
T45	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1958946072			Jun 21 08:16:59 PM PDT 24	Jun 21 08:25:33 PM PDT 24	5998273132 ps
T200	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3301898426			Jun 21 08:03:18 PM PDT 24	Jun 21 08:32:27 PM PDT 24	8557122664 ps
T286	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3645955080			Jun 21 08:02:55 PM PDT 24	Jun 21 08:05:37 PM PDT 24	2422334500 ps
T52	/workspace/coverage/default/0.rom_e2e_smoke.3712385118			Jun 21 08:04:45 PM PDT 24	Jun 21 09:08:19 PM PDT 24	15131842500 ps
T203	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.438685225			Jun 21 08:03:20 PM PDT 24	Jun 21 08:13:32 PM PDT 24	3991980366 ps
T24	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3541975179			Jun 21 07:57:58 PM PDT 24	Jun 21 08:06:54 PM PDT 24	3844477351 ps
T686	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.315481633			Jun 21 08:32:06 PM PDT 24	Jun 21 08:37:11 PM PDT 24	3087510590 ps
T190	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3250183192			Jun 21 08:18:32 PM PDT 24	Jun 21 08:30:52 PM PDT 24	5381081175 ps
T64	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2763554365			Jun 21 08:25:14 PM PDT 24	Jun 21 08:37:21 PM PDT 24	6283056339 ps
T117	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1685678077			Jun 21 08:01:59 PM PDT 24	Jun 21 08:16:44 PM PDT 24	6932317392 ps
T31	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1946971624			Jun 21 08:16:56 PM PDT 24	Jun 21 09:08:41 PM PDT 24	20312369164 ps
T62	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1966377345			Jun 21 08:04:32 PM PDT 24	Jun 21 09:35:17 PM PDT 24	51292487876 ps
T680	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1038435797			Jun 21 07:57:40 PM PDT 24	Jun 21 08:04:17 PM PDT 24	5596044328 ps
T121	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.292604033			Jun 21 08:19:38 PM PDT 24	Jun 21 08:38:05 PM PDT 24	5188347032 ps
T114	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.523044151			Jun 21 07:59:42 PM PDT 24	Jun 21 08:10:31 PM PDT 24	4976223680 ps
T394	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709205179			Jun 21 08:27:55 PM PDT 24	Jun 21 08:35:29 PM PDT 24	3223070526 ps
T687	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2730011582			Jun 21 08:32:33 PM PDT 24	Jun 21 08:38:09 PM PDT 24	3312794614 ps
T358	/workspace/coverage/default/33.chip_sw_all_escalation_resets.1849909776			Jun 21 08:30:43 PM PDT 24	Jun 21 08:41:07 PM PDT 24	6190401400 ps
T108	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2124656198			Jun 21 08:04:01 PM PDT 24	Jun 21 09:07:03 PM PDT 24	21214463105 ps
T253	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2798967097			Jun 21 08:29:00 PM PDT 24	Jun 21 08:39:28 PM PDT 24	4533385320 ps
T250	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4102933959			Jun 21 08:33:02 PM PDT 24	Jun 21 09:25:20 PM PDT 24	16009907588 ps
T158	/workspace/coverage/default/0.rom_volatile_raw_unlock.432661204			Jun 21 08:04:15 PM PDT 24	Jun 21 08:06:15 PM PDT 24	2504501002 ps
T181	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1953698985			Jun 21 08:04:14 PM PDT 24	Jun 21 08:06:17 PM PDT 24	2527763697 ps
T53	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3407058436			Jun 21 08:06:31 PM PDT 24	Jun 21 09:35:48 PM PDT 24	24833192888 ps
T463	/workspace/coverage/default/1.chip_sw_kmac_entropy.816832576			Jun 21 08:02:30 PM PDT 24	Jun 21 08:07:14 PM PDT 24	3187961260 ps
T462	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2766143482			Jun 21 08:01:14 PM PDT 24	Jun 21 08:20:50 PM PDT 24	5500621392 ps
T464	/workspace/coverage/default/2.chip_sw_kmac_idle.4044184070			Jun 21 08:19:10 PM PDT 24	Jun 21 08:23:30 PM PDT 24	2847523496 ps
T204	/workspace/coverage/default/0.chip_sw_pattgen_ios.3481382317			Jun 21 08:02:02 PM PDT 24	Jun 21 08:05:56 PM PDT 24	2189224632 ps
T369	/workspace/coverage/default/34.chip_sw_all_escalation_resets.43099305			Jun 21 08:29:49 PM PDT 24	Jun 21 08:39:53 PM PDT 24	5679574212 ps
T251	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1698259723			Jun 21 08:19:41 PM PDT 24	Jun 21 09:31:11 PM PDT 24	19400616090 ps
T115	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.129626400			Jun 21 08:16:05 PM PDT 24	Jun 21 08:24:33 PM PDT 24	4072846481 ps
T235	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4146417734			Jun 21 08:03:07 PM PDT 24	Jun 21 08:05:25 PM PDT 24	2716283720 ps
T414	/workspace/coverage/default/0.rom_e2e_static_critical.1904364305			Jun 21 08:07:39 PM PDT 24	Jun 21 09:27:51 PM PDT 24	17847794604 ps
T67	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3761732082			Jun 21 08:12:11 PM PDT 24	Jun 21 08:20:51 PM PDT 24	4569583944 ps
T68	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3982597293			Jun 21 08:12:17 PM PDT 24	Jun 21 08:21:03 PM PDT 24	5196129835 ps
T198	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1256872821			Jun 21 08:18:22 PM PDT 24	Jun 21 08:22:09 PM PDT 24	2312256184 ps
T202	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1849071737			Jun 21 08:01:48 PM PDT 24	Jun 21 08:25:13 PM PDT 24	8478640212 ps
T201	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3792971510			Jun 21 08:28:21 PM PDT 24	Jun 21 08:37:54 PM PDT 24	3726950084 ps
T325	/workspace/coverage/default/0.chip_sw_hmac_enc.1125263895			Jun 21 07:59:54 PM PDT 24	Jun 21 08:04:07 PM PDT 24	2636986140 ps
T153	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2839690994			Jun 21 08:02:16 PM PDT 24	Jun 21 11:36:38 PM PDT 24	255477838332 ps
T366	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2870472821			Jun 21 07:58:39 PM PDT 24	Jun 21 08:32:21 PM PDT 24	13437864207 ps
T199	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2663087821			Jun 21 08:27:48 PM PDT 24	Jun 21 08:33:58 PM PDT 24	3291720196 ps
T895	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1026106897			Jun 21 07:58:52 PM PDT 24	Jun 21 08:02:23 PM PDT 24	2640795093 ps
T370	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1363951176			Jun 21 08:28:23 PM PDT 24	Jun 21 08:40:31 PM PDT 24	6269456950 ps
T206	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1602740189			Jun 21 08:06:52 PM PDT 24	Jun 21 09:12:24 PM PDT 24	15528344386 ps
T69	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.805141996			Jun 21 08:23:01 PM PDT 24	Jun 21 08:32:37 PM PDT 24	4914763023 ps
T457	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.425258706			Jun 21 08:02:03 PM PDT 24	Jun 21 08:05:36 PM PDT 24	2572291458 ps
T122	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3656432587			Jun 21 08:12:15 PM PDT 24	Jun 21 08:19:15 PM PDT 24	5525725672 ps
T70	/workspace/coverage/default/1.chip_tap_straps_prod.2538625300			Jun 21 08:10:32 PM PDT 24	Jun 21 08:21:43 PM PDT 24	6671302484 ps
T896	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4273581218			Jun 21 08:00:57 PM PDT 24	Jun 21 08:04:42 PM PDT 24	3662978408 ps
T80	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3728463949			Jun 21 08:31:43 PM PDT 24	Jun 21 08:39:49 PM PDT 24	4341317162 ps
T93	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2684872644			Jun 21 08:33:02 PM PDT 24	Jun 21 08:44:59 PM PDT 24	3771758744 ps
T32	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3496052094			Jun 21 08:09:30 PM PDT 24	Jun 21 09:00:38 PM PDT 24	20168051980 ps
T7	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1584703531			Jun 21 08:13:08 PM PDT 24	Jun 21 08:18:34 PM PDT 24	3791348604 ps
T94	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1592746873			Jun 21 08:32:35 PM PDT 24	Jun 21 08:38:24 PM PDT 24	3610724344 ps
T95	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.647321454			Jun 21 07:58:40 PM PDT 24	Jun 21 08:07:52 PM PDT 24	18914738264 ps
T96	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.249140586			Jun 21 08:05:31 PM PDT 24	Jun 21 09:10:46 PM PDT 24	15446002550 ps
T97	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1016431897			Jun 21 08:18:48 PM PDT 24	Jun 21 08:40:16 PM PDT 24	7004067440 ps
T98	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3049067748			Jun 21 08:12:06 PM PDT 24	Jun 21 08:18:29 PM PDT 24	3163443760 ps
T99	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1682754373			Jun 21 08:23:40 PM PDT 24	Jun 21 09:39:18 PM PDT 24	15162876854 ps
T453	/workspace/coverage/default/20.chip_sw_all_escalation_resets.832432342			Jun 21 08:28:22 PM PDT 24	Jun 21 08:37:12 PM PDT 24	4405427398 ps
T112	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.551562015			Jun 21 08:01:00 PM PDT 24	Jun 21 08:09:29 PM PDT 24	4603179631 ps
T367	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2734240856			Jun 21 08:03:35 PM PDT 24	Jun 21 08:24:03 PM PDT 24	8732822223 ps
T205	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2892810389			Jun 21 08:03:51 PM PDT 24	Jun 21 08:13:37 PM PDT 24	4462022266 ps
T28	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3321296648			Jun 21 08:14:49 PM PDT 24	Jun 21 08:24:25 PM PDT 24	4802487508 ps
T715	/workspace/coverage/default/2.chip_sw_hmac_multistream.3109951947			Jun 21 08:19:29 PM PDT 24	Jun 21 08:48:35 PM PDT 24	6518236290 ps
T170	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1770063973			Jun 21 08:12:04 PM PDT 24	Jun 21 08:14:43 PM PDT 24	2089495536 ps
T248	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3558861058			Jun 21 08:16:51 PM PDT 24	Jun 21 08:39:08 PM PDT 24	17840470024 ps
T299	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2976312339			Jun 21 08:29:13 PM PDT 24	Jun 21 08:38:47 PM PDT 24	4418420970 ps
T29	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3742485504			Jun 21 08:26:34 PM PDT 24	Jun 21 08:37:02 PM PDT 24	4679811206 ps
T300	/workspace/coverage/default/54.chip_sw_all_escalation_resets.4215955101			Jun 21 08:32:49 PM PDT 24	Jun 21 08:42:05 PM PDT 24	5210453640 ps
T154	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2514138744			Jun 21 08:27:54 PM PDT 24	Jun 21 08:36:07 PM PDT 24	3661621944 ps
T301	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.306082691			Jun 21 08:00:54 PM PDT 24	Jun 21 08:12:57 PM PDT 24	4603903266 ps
T163	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3702716973			Jun 21 08:15:11 PM PDT 24	Jun 21 09:39:50 PM PDT 24	44184217077 ps
T48	/workspace/coverage/default/2.chip_sw_spi_device_tpm.4100305300			Jun 21 08:15:10 PM PDT 24	Jun 21 08:22:34 PM PDT 24	3231547055 ps
T302	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3240004368			Jun 21 08:36:16 PM PDT 24	Jun 21 08:48:02 PM PDT 24	5521985652 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3733904005			Jun 21 08:11:40 PM PDT 24	Jun 21 08:31:22 PM PDT 24	21868360168 ps
T101	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.858558323			Jun 21 08:17:10 PM PDT 24	Jun 21 08:29:40 PM PDT 24	7146203203 ps
T102	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3301194225			Jun 21 08:28:39 PM PDT 24	Jun 21 08:34:20 PM PDT 24	3331357592 ps
T103	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.197889347			Jun 21 08:00:15 PM PDT 24	Jun 21 08:11:48 PM PDT 24	4818372420 ps
T71	/workspace/coverage/default/4.chip_tap_straps_prod.19828749			Jun 21 08:25:16 PM PDT 24	Jun 21 08:50:32 PM PDT 24	16867687818 ps
T104	/workspace/coverage/default/2.chip_sw_hmac_smoketest.107891155			Jun 21 08:24:32 PM PDT 24	Jun 21 08:29:37 PM PDT 24	2650609280 ps
T105	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3833886825			Jun 21 08:02:55 PM PDT 24	Jun 21 09:06:19 PM PDT 24	27571984860 ps
T106	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2861765079			Jun 21 08:26:26 PM PDT 24	Jun 21 08:39:21 PM PDT 24	13319848499 ps
T81	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3939187153			Jun 21 07:58:51 PM PDT 24	Jun 21 08:19:06 PM PDT 24	12408265214 ps
T107	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3072154070			Jun 21 08:29:36 PM PDT 24	Jun 21 08:35:54 PM PDT 24	3804734214 ps
T138	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1453494844			Jun 21 08:15:22 PM PDT 24	Jun 21 11:30:14 PM PDT 24	64041230469 ps
T897	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1069379165			Jun 21 08:19:37 PM PDT 24	Jun 21 08:25:09 PM PDT 24	3111644811 ps
T898	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3711231798			Jun 21 08:26:41 PM PDT 24	Jun 21 08:33:15 PM PDT 24	3626673532 ps
T160	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3178882537			Jun 21 08:17:15 PM PDT 24	Jun 21 08:36:10 PM PDT 24	11539975916 ps
T386	/workspace/coverage/default/2.rom_e2e_asm_init_prod.3406894739			Jun 21 08:27:49 PM PDT 24	Jun 21 09:30:11 PM PDT 24	15874081292 ps
T207	/workspace/coverage/default/76.chip_sw_all_escalation_resets.4189911620			Jun 21 08:33:19 PM PDT 24	Jun 21 08:45:27 PM PDT 24	5459884000 ps
T899	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3965970616			Jun 21 08:00:39 PM PDT 24	Jun 21 08:16:25 PM PDT 24	9136189479 ps
T900	/workspace/coverage/default/2.chip_sw_uart_smoketest.4237643561			Jun 21 08:23:49 PM PDT 24	Jun 21 08:28:53 PM PDT 24	3005287512 ps
T77	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2280250279			Jun 21 08:01:23 PM PDT 24	Jun 21 08:07:52 PM PDT 24	5236114832 ps
T142	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1243195284			Jun 21 08:28:00 PM PDT 24	Jun 21 08:49:23 PM PDT 24	7853453418 ps
T387	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1701875045			Jun 21 08:22:35 PM PDT 24	Jun 21 09:41:22 PM PDT 24	16054600088 ps
T688	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599131669			Jun 21 08:31:16 PM PDT 24	Jun 21 08:35:50 PM PDT 24	3589615616 ps
T789	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3127087585			Jun 21 08:30:25 PM PDT 24	Jun 21 08:37:18 PM PDT 24	4319647124 ps
T901	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.89707337			Jun 21 08:11:14 PM PDT 24	Jun 21 08:14:05 PM PDT 24	2434709539 ps
T116	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.187550239			Jun 21 08:20:35 PM PDT 24	Jun 21 08:32:00 PM PDT 24	4335413490 ps
T685	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2289687624			Jun 21 08:07:13 PM PDT 24	Jun 21 08:22:41 PM PDT 24	5567686848 ps
T902	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1254127964			Jun 21 07:59:51 PM PDT 24	Jun 21 08:05:21 PM PDT 24	3236153348 ps
T402	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.463718351			Jun 21 08:02:20 PM PDT 24	Jun 21 08:11:24 PM PDT 24	5436729268 ps
T143	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3249596711			Jun 21 08:06:43 PM PDT 24	Jun 21 08:17:39 PM PDT 24	4436857444 ps
T355	/workspace/coverage/default/50.chip_sw_all_escalation_resets.392442150			Jun 21 08:31:58 PM PDT 24	Jun 21 08:41:02 PM PDT 24	6532953368 ps
T356	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2601017188			Jun 21 08:32:00 PM PDT 24	Jun 21 08:43:25 PM PDT 24	5108262530 ps
T903	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3729391500			Jun 21 08:01:25 PM PDT 24	Jun 21 08:10:41 PM PDT 24	5169402768 ps
T410	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2553515673			Jun 21 08:19:50 PM PDT 24	Jun 21 08:51:00 PM PDT 24	8953060104 ps
T320	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1913508216			Jun 21 08:31:21 PM PDT 24	Jun 21 08:42:45 PM PDT 24	4482597840 ps
T783	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172137283			Jun 21 08:32:26 PM PDT 24	Jun 21 08:37:35 PM PDT 24	2921267550 ps
T264	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1253085101			Jun 21 08:02:37 PM PDT 24	Jun 21 08:04:32 PM PDT 24	2905939747 ps
T904	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2887831312			Jun 21 08:10:18 PM PDT 24	Jun 21 08:21:19 PM PDT 24	4044018606 ps
T208	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2304709781			Jun 21 08:10:03 PM PDT 24	Jun 21 08:58:26 PM PDT 24	10490086820 ps
T905	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.589629343			Jun 21 08:04:45 PM PDT 24	Jun 21 08:22:34 PM PDT 24	5665649858 ps
T906	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2646759450			Jun 21 08:03:51 PM PDT 24	Jun 21 08:11:45 PM PDT 24	4498893978 ps
T907	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2080564864			Jun 21 08:11:51 PM PDT 24	Jun 21 08:15:43 PM PDT 24	2757260376 ps
T309	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2561848163			Jun 21 08:29:26 PM PDT 24	Jun 21 08:37:28 PM PDT 24	5899172720 ps
T314	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3792233537			Jun 21 08:25:22 PM PDT 24	Jun 21 08:43:56 PM PDT 24	12570092230 ps
T315	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2369118978			Jun 21 08:07:24 PM PDT 24	Jun 21 08:15:19 PM PDT 24	3546045700 ps
T316	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1255486558			Jun 21 08:09:35 PM PDT 24	Jun 21 08:20:43 PM PDT 24	4855306470 ps
T317	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1019480427			Jun 21 08:08:42 PM PDT 24	Jun 21 08:22:40 PM PDT 24	8038062088 ps
T318	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3706664103			Jun 21 07:58:42 PM PDT 24	Jun 21 08:04:18 PM PDT 24	3776514472 ps
T244	/workspace/coverage/default/0.chip_sw_rv_timer_irq.3735043055			Jun 21 07:59:22 PM PDT 24	Jun 21 08:03:38 PM PDT 24	3269773138 ps
T265	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1089801112			Jun 21 08:15:47 PM PDT 24	Jun 21 08:17:34 PM PDT 24	2238445316 ps
T319	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4076279196			Jun 21 08:03:49 PM PDT 24	Jun 21 08:07:05 PM PDT 24	2987362406 ps
T307	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.680403738			Jun 21 08:00:29 PM PDT 24	Jun 21 08:21:28 PM PDT 24	9599424084 ps
T908	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3637118756			Jun 21 08:23:53 PM PDT 24	Jun 21 08:28:09 PM PDT 24	3718281197 ps
T359	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1844531395			Jun 21 08:32:35 PM PDT 24	Jun 21 08:43:09 PM PDT 24	4308296576 ps
T415	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1337320606			Jun 21 08:09:26 PM PDT 24	Jun 21 08:14:12 PM PDT 24	3150445050 ps
T400	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.608810676			Jun 21 08:23:19 PM PDT 24	Jun 21 08:28:08 PM PDT 24	2560582078 ps
T321	/workspace/coverage/default/1.chip_plic_all_irqs_0.4103092126			Jun 21 08:09:18 PM PDT 24	Jun 21 08:32:23 PM PDT 24	5644666320 ps
T909	/workspace/coverage/default/2.chip_sw_hmac_oneshot.3515220176			Jun 21 08:19:42 PM PDT 24	Jun 21 08:26:20 PM PDT 24	3552157618 ps
T245	/workspace/coverage/default/1.chip_sw_rv_timer_irq.3511732292			Jun 21 08:05:39 PM PDT 24	Jun 21 08:09:46 PM PDT 24	2578776306 ps
T910	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3488042415			Jun 21 08:06:46 PM PDT 24	Jun 21 08:11:37 PM PDT 24	3554584510 ps
T728	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3539853907			Jun 21 08:20:29 PM PDT 24	Jun 21 08:52:38 PM PDT 24	25294992282 ps
T2	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.911362988			Jun 21 08:11:08 PM PDT 24	Jun 21 08:46:02 PM PDT 24	23583946770 ps
T911	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3778492951			Jun 21 08:00:00 PM PDT 24	Jun 21 08:03:18 PM PDT 24	2987255928 ps
T171	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.4268009313			Jun 21 08:12:01 PM PDT 24	Jun 21 08:15:51 PM PDT 24	3372923384 ps
T405	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2426973226			Jun 21 08:28:05 PM PDT 24	Jun 21 08:35:13 PM PDT 24	3448012080 ps
T144	/workspace/coverage/default/1.chip_sw_otbn_smoketest.582081906			Jun 21 08:13:21 PM PDT 24	Jun 21 08:32:40 PM PDT 24	5684808232 ps
T82	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.958313992			Jun 21 08:18:56 PM PDT 24	Jun 21 08:44:15 PM PDT 24	11393202456 ps
T406	/workspace/coverage/default/2.chip_sw_flash_crash_alert.1490415834			Jun 21 08:24:09 PM PDT 24	Jun 21 08:38:40 PM PDT 24	5961365416 ps
T407	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3698542245			Jun 21 08:15:59 PM PDT 24	Jun 21 08:21:15 PM PDT 24	2909705788 ps
T166	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3492794501			Jun 21 08:01:08 PM PDT 24	Jun 21 08:04:04 PM PDT 24	3771592269 ps
T408	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1072589858			Jun 21 08:25:18 PM PDT 24	Jun 21 08:32:33 PM PDT 24	6072994120 ps
T409	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1253101564			Jun 21 07:59:44 PM PDT 24	Jun 21 08:02:19 PM PDT 24	2577810580 ps
T191	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2410844208			Jun 21 07:59:31 PM PDT 24	Jun 21 08:04:44 PM PDT 24	3152731682 ps
T912	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.701746620			Jun 21 08:06:46 PM PDT 24	Jun 21 09:05:33 PM PDT 24	11504052504 ps
T913	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3017455243			Jun 21 08:11:24 PM PDT 24	Jun 21 08:17:14 PM PDT 24	4538907512 ps
T914	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.360292797			Jun 21 08:00:47 PM PDT 24	Jun 21 08:06:04 PM PDT 24	3386548954 ps
T339	/workspace/coverage/default/2.chip_sw_otbn_randomness.1178229926			Jun 21 08:18:33 PM PDT 24	Jun 21 08:35:25 PM PDT 24	6478110120 ps
T33	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3415219979			Jun 21 08:16:44 PM PDT 24	Jun 21 08:23:59 PM PDT 24	3844441360 ps
T109	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3154208127			Jun 21 08:24:12 PM PDT 24	Jun 21 08:50:28 PM PDT 24	11649032625 ps
T323	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1110569972			Jun 21 08:24:05 PM PDT 24	Jun 21 08:32:49 PM PDT 24	4338739220 ps
T915	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3168381746			Jun 21 08:01:44 PM PDT 24	Jun 21 08:12:50 PM PDT 24	4039119176 ps
T750	/workspace/coverage/default/28.chip_sw_all_escalation_resets.842756120			Jun 21 08:28:53 PM PDT 24	Jun 21 08:41:21 PM PDT 24	4333722652 ps
T916	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.214308278			Jun 21 08:10:22 PM PDT 24	Jun 21 08:23:12 PM PDT 24	4377022504 ps
T917	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3249075772			Jun 21 08:05:18 PM PDT 24	Jun 21 08:16:14 PM PDT 24	4214347576 ps
T376	/workspace/coverage/default/0.chip_tap_straps_dev.705282389			Jun 21 08:02:10 PM PDT 24	Jun 21 08:32:03 PM PDT 24	14451571875 ps
T209	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4152940609			Jun 21 08:08:31 PM PDT 24	Jun 21 08:35:54 PM PDT 24	8988024680 ps
T164	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1330378884			Jun 21 08:17:14 PM PDT 24	Jun 21 09:49:58 PM PDT 24	51002269180 ps
T918	/workspace/coverage/default/1.chip_sw_example_concurrency.2087211324			Jun 21 08:02:44 PM PDT 24	Jun 21 08:05:51 PM PDT 24	2619189800 ps
T790	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.506883251			Jun 21 08:28:26 PM PDT 24	Jun 21 08:33:59 PM PDT 24	3732988968 ps
T210	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2682623361			Jun 21 08:18:25 PM PDT 24	Jun 21 08:30:53 PM PDT 24	4857839400 ps
T231	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1735721228			Jun 21 08:25:35 PM PDT 24	Jun 21 08:40:17 PM PDT 24	6930015560 ps
T270	/workspace/coverage/default/90.chip_sw_all_escalation_resets.1943512881			Jun 21 08:35:32 PM PDT 24	Jun 21 08:43:46 PM PDT 24	6028421008 ps
T188	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3440896961			Jun 21 08:04:01 PM PDT 24	Jun 21 11:54:51 PM PDT 24	78138970350 ps
T271	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3247470055			Jun 21 08:20:41 PM PDT 24	Jun 21 08:30:59 PM PDT 24	5439342846 ps
T211	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2232587482			Jun 21 08:09:21 PM PDT 24	Jun 21 08:33:52 PM PDT 24	8955758512 ps
T272	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.326369094			Jun 21 08:20:24 PM PDT 24	Jun 21 08:32:36 PM PDT 24	5090291128 ps
T25	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3472478596			Jun 21 08:15:37 PM PDT 24	Jun 21 08:23:38 PM PDT 24	3904169486 ps
T273	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2320719305			Jun 21 08:22:13 PM PDT 24	Jun 21 08:42:46 PM PDT 24	7248184653 ps
T274	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1372552549			Jun 21 08:01:11 PM PDT 24	Jun 21 08:23:54 PM PDT 24	9904238912 ps
T275	/workspace/coverage/default/4.chip_sw_uart_tx_rx.3113299485			Jun 21 08:24:47 PM PDT 24	Jun 21 08:35:30 PM PDT 24	3989115710 ps
T161	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2693524907			Jun 21 08:34:10 PM PDT 24	Jun 21 08:47:22 PM PDT 24	5741438280 ps
T368	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4077283555			Jun 21 08:25:16 PM PDT 24	Jun 21 08:38:37 PM PDT 24	4725491928 ps
T919	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.753851808			Jun 21 08:00:39 PM PDT 24	Jun 21 08:10:27 PM PDT 24	4335205452 ps
T416	/workspace/coverage/default/12.chip_sw_all_escalation_resets.791993773			Jun 21 08:28:08 PM PDT 24	Jun 21 08:39:57 PM PDT 24	5350536504 ps
T749	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1901911784			Jun 21 08:32:37 PM PDT 24	Jun 21 08:37:21 PM PDT 24	3539975624 ps
T146	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3905265065			Jun 21 08:16:43 PM PDT 24	Jun 21 11:27:25 PM PDT 24	58355208154 ps
T920	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1169200286			Jun 21 08:12:35 PM PDT 24	Jun 21 08:18:44 PM PDT 24	3248954156 ps
T921	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2946850399			Jun 21 08:12:42 PM PDT 24	Jun 21 08:17:07 PM PDT 24	3044994020 ps
T922	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2419254033			Jun 21 08:01:17 PM PDT 24	Jun 21 08:06:04 PM PDT 24	3090901837 ps
T923	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3986032856			Jun 21 08:06:52 PM PDT 24	Jun 21 09:12:35 PM PDT 24	15776480600 ps
T556	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3256209680			Jun 21 08:18:11 PM PDT 24	Jun 21 08:33:30 PM PDT 24	4973962548 ps
T771	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2213121893			Jun 21 08:32:12 PM PDT 24	Jun 21 08:37:56 PM PDT 24	3555483424 ps
T212	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1729259131			Jun 21 07:59:18 PM PDT 24	Jun 21 08:23:25 PM PDT 24	7640378492 ps
T169	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2306730443			Jun 21 08:20:01 PM PDT 24	Jun 21 08:34:29 PM PDT 24	9374193550 ps
T759	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836922216			Jun 21 08:31:21 PM PDT 24	Jun 21 08:36:28 PM PDT 24	3778614696 ps
T924	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1273761521			Jun 21 08:25:45 PM PDT 24	Jun 21 08:38:11 PM PDT 24	4361454738 ps
T925	/workspace/coverage/default/1.chip_sw_hmac_multistream.375325692			Jun 21 08:08:13 PM PDT 24	Jun 21 08:35:15 PM PDT 24	6474977400 ps
T417	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3616851744			Jun 21 08:01:51 PM PDT 24	Jun 21 09:32:26 PM PDT 24	42894261900 ps
T760	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2571011839			Jun 21 08:33:44 PM PDT 24	Jun 21 08:39:42 PM PDT 24	3587406720 ps
T123	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.485317103			Jun 21 08:10:16 PM PDT 24	Jun 21 08:18:53 PM PDT 24	5119530114 ps
T735	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3723421564			Jun 21 08:29:48 PM PDT 24	Jun 21 08:39:22 PM PDT 24	5019584126 ps
T926	/workspace/coverage/default/1.chip_sw_aes_enc.1811321686			Jun 21 08:06:07 PM PDT 24	Jun 21 08:10:33 PM PDT 24	3321606488 ps
T927	/workspace/coverage/default/1.chip_sw_example_flash.2298809549			Jun 21 08:06:47 PM PDT 24	Jun 21 08:10:25 PM PDT 24	2780070024 ps
T350	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2527249985			Jun 21 08:07:44 PM PDT 24	Jun 21 08:18:20 PM PDT 24	4060934570 ps
T928	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2868581750			Jun 21 08:02:46 PM PDT 24	Jun 21 08:20:08 PM PDT 24	9734564911 ps
T929	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3172271830			Jun 21 08:29:36 PM PDT 24	Jun 21 08:41:49 PM PDT 24	4557309222 ps
T118	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1936313434			Jun 21 08:00:44 PM PDT 24	Jun 21 08:10:44 PM PDT 24	6879394664 ps
T236	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2068787978			Jun 21 08:33:56 PM PDT 24	Jun 21 08:39:13 PM PDT 24	3655539718 ps
T289	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.4103041945			Jun 21 08:00:19 PM PDT 24	Jun 21 08:50:55 PM PDT 24	13011197760 ps
T290	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2087195776			Jun 21 08:20:35 PM PDT 24	Jun 21 08:30:31 PM PDT 24	3803811120 ps
T26	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1811295153			Jun 21 08:03:42 PM PDT 24	Jun 21 08:13:10 PM PDT 24	4720634316 ps
T291	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1159688137			Jun 21 08:12:11 PM PDT 24	Jun 21 08:32:07 PM PDT 24	7983827668 ps
T292	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2538805776			Jun 21 08:20:53 PM PDT 24	Jun 21 08:28:25 PM PDT 24	3468803140 ps
T293	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3830652473			Jun 21 08:06:25 PM PDT 24	Jun 21 09:08:01 PM PDT 24	16002796446 ps
T294	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1344274542			Jun 21 08:25:45 PM PDT 24	Jun 21 08:38:13 PM PDT 24	5985858264 ps
T119	/workspace/coverage/default/0.chip_sw_edn_kat.500447099			Jun 21 08:01:57 PM PDT 24	Jun 21 08:13:54 PM PDT 24	3268340672 ps
T295	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172400737			Jun 21 08:34:52 PM PDT 24	Jun 21 08:41:03 PM PDT 24	4197726008 ps
T816	/workspace/coverage/default/57.chip_sw_all_escalation_resets.609447908			Jun 21 08:32:29 PM PDT 24	Jun 21 08:41:00 PM PDT 24	5338735392 ps
T930	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3881968223			Jun 21 08:10:49 PM PDT 24	Jun 21 08:20:56 PM PDT 24	4437750740 ps
T802	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.391514972			Jun 21 08:27:37 PM PDT 24	Jun 21 08:34:34 PM PDT 24	3324394928 ps