Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3705	1			T75	5		T79	9		T249	11
all_values[1]	3643	1			T75	7		T79	16		T249	5
all_values[2]	3633	1			T75	7		T79	18		T249	6
all_values[3]	3703	1			T75	1		T79	17		T249	8
all_values[4]	3669	1			T75	2		T79	20		T249	4
all_values[5]	3728	1			T75	5		T79	18		T249	5
all_values[6]	3815	1			T75	10		T79	9		T249	9
all_values[7]	3727	1			T75	3		T79	22		T249	10
all_values[8]	3752	1			T75	4		T79	23		T249	4
all_values[9]	3743	1			T75	8		T79	9		T249	3
all_values[10]	3617	1			T75	8		T79	9		T249	5
all_values[11]	3673	1			T75	3		T79	15		T249	6
all_values[12]	3837	1			T75	6		T79	16		T249	9
all_values[13]	3620	1			T75	2		T79	14		T249	9
all_values[14]	3668	1			T75	5		T79	12		T249	4
all_values[15]	3705	1			T75	6		T79	9		T249	13
all_values[16]	3828	1			T75	3		T79	20		T249	4
all_values[17]	3738	1			T75	4		T79	12		T249	3
all_values[18]	3668	1			T75	6		T79	17		T249	9
all_values[19]	3668	1			T75	5		T79	12		T249	7
all_values[20]	3706	1			T75	3		T79	16		T249	11
all_values[21]	3786	1			T75	7		T79	21		T249	6
all_values[22]	3598	1			T75	6		T79	10		T249	9
all_values[23]	3655	1			T75	4		T79	15		T249	5
all_values[24]	3747	1			T75	5		T79	18		T249	6
all_values[25]	3613	1			T75	5		T79	13		T249	9
all_values[26]	3821	1			T75	6		T79	16		T249	5
all_values[27]	3618	1			T75	7		T79	24		T249	3
all_values[28]	3768	1			T75	4		T79	12		T249	6
all_values[29]	3830	1			T75	10		T79	21		T249	6
all_values[30]	3685	1			T75	2		T79	13		T249	3
all_values[31]	3755	1			T75	4		T79	15		T249	7
all_values[32]	3714	1			T75	6		T79	11		T249	11
all_values[33]	3653	1			T75	4		T79	12		T249	8
all_values[34]	3743	1			T75	4		T79	12		T249	10
all_values[35]	3714	1			T75	10		T79	8		T249	6
all_values[36]	3751	1			T75	7		T79	20		T249	7
all_values[37]	3691	1			T75	4		T79	22		T249	8
all_values[38]	3699	1			T75	9		T79	18		T249	2
all_values[39]	3679	1			T75	7		T79	12		T249	6
all_values[40]	3763	1			T75	6		T79	18		T249	10
all_values[41]	3712	1			T75	7		T79	12		T249	7
all_values[42]	3719	1			T75	4		T79	12		T249	7
all_values[43]	3727	1			T75	3		T79	19		T249	8
all_values[44]	3769	1			T75	5		T79	14		T249	6
all_values[45]	3742	1			T75	2		T79	18		T249	9
all_values[46]	3647	1			T75	9		T79	16		T249	6
all_values[47]	3738	1			T75	11		T79	19		T249	8
all_values[48]	3652	1			T75	4		T79	17		T249	6
all_values[49]	3687	1			T75	5		T79	12		T249	7
all_values[50]	3597	1			T75	2		T79	19		T249	7
all_values[51]	3663	1			T75	7		T79	14		T249	8
all_values[52]	3696	1			T75	6		T79	18		T249	2
all_values[53]	3682	1			T75	6		T79	17		T249	9
all_values[54]	3631	1			T75	3		T79	9		T249	7
all_values[55]	3739	1			T75	2		T79	21		T249	3
all_values[56]	3597	1			T75	6		T79	13		T249	11
all_values[57]	3730	1			T75	5		T79	17		T249	8
all_values[58]	3820	1			T75	4		T79	23		T249	7
all_values[59]	3694	1			T75	4		T79	19		T249	10
all_values[60]	3702	1			T75	4		T79	10		T249	6
all_values[61]	3730	1			T75	3		T79	10		T249	9
all_values[62]	3686	1			T75	5		T79	8		T249	9
all_values[63]	3737	1			T75	5		T79	23		T249	7