Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145968	1			T70	2		T71	109		T72	306
values[2]	10338	1			T71	8		T72	5		T356	7
values[3]	3766	1			T71	7		T508	23		T587	36
values[4]	2105	1			T71	4		T508	3		T587	20
values[5]	1344	1			T71	4		T508	3		T500	3
values[6]	928	1			T71	16		T508	6		T500	3
values[7]	633	1			T71	7		T508	12		T500	4
values[8]	489	1			T71	18		T508	6		T500	1
values[9]	500	1			T71	3		T500	4		T577	5
values[10]	471	1			T71	7		T500	5		T577	7
values[11]	380	1			T71	7		T500	2		T577	9
values[12]	330	1			T71	2		T500	1		T577	13
values[13]	304	1			T71	4		T500	2		T577	9
values[14]	304	1			T71	17		T500	3		T577	7
values[15]	276	1			T71	7		T500	4		T577	3
values[16]	300	1			T71	6		T500	3		T577	2
values[17]	290	1			T71	11		T500	8		T577	5
values[18]	286	1			T71	11		T500	16		T577	9
values[19]	247	1			T71	3		T500	6		T577	4
values[20]	252	1			T71	6		T500	8		T577	9
values[21]	244	1			T71	11		T500	6		T577	6
values[22]	266	1			T71	9		T500	2		T577	6
values[23]	226	1			T71	6		T500	2		T577	7
values[24]	293	1			T71	5		T500	7		T577	4
values[25]	262	1			T71	3		T500	5		T577	7
values[26]	292	1			T71	4		T500	3		T577	6
values[27]	337	1			T71	7		T500	2		T577	6
values[28]	232	1			T71	7		T500	1		T577	5
values[29]	255	1			T71	5		T500	3		T577	6
values[30]	227	1			T71	16		T500	1		T577	8
values[31]	279	1			T71	22		T500	1		T577	6
values[32]	239	1			T71	11		T500	2		T577	4
values[33]	235	1			T71	9		T500	1		T577	11
values[34]	222	1			T71	4		T500	1		T577	7
values[35]	241	1			T71	5		T500	3		T577	6
values[36]	221	1			T71	4		T500	1		T577	5
values[37]	211	1			T71	8		T500	3		T577	7
values[38]	203	1			T71	4		T500	2		T577	5
values[39]	225	1			T71	11		T500	1		T577	8
values[40]	262	1			T71	20		T500	3		T577	11
values[41]	268	1			T71	5		T500	3		T577	15
values[42]	235	1			T71	11		T500	3		T577	6
values[43]	272	1			T71	2		T500	2		T577	4
values[44]	239	1			T71	13		T500	2		T577	15
values[45]	208	1			T71	7		T500	1		T577	15
values[46]	227	1			T71	2		T500	6		T577	8
values[47]	208	1			T71	6		T500	2		T577	5
values[48]	236	1			T71	13		T500	4		T577	15
values[49]	211	1			T71	2		T500	1		T577	16
values[50]	214	1			T71	9		T500	4		T577	6
values[51]	162	1			T71	7		T500	3		T577	5
values[52]	163	1			T71	4		T500	2		T577	3
values[53]	173	1			T71	6		T500	1		T577	16
values[54]	192	1			T71	3		T500	2		T577	12
values[55]	170	1			T71	13		T500	3		T577	5
values[56]	194	1			T71	3		T500	3		T577	20
values[57]	158	1			T71	10		T500	6		T577	7
values[58]	143	1			T71	11		T500	1		T577	8
values[59]	154	1			T71	12		T500	2		T577	4
values[60]	153	1			T71	11		T500	4		T577	7
values[61]	129	1			T71	15		T500	5		T577	4
values[62]	107	1			T71	7		T500	2		T577	5
values[63]	95	1			T71	8		T500	1		T577	4
values[64]	106	1			T71	8		T500	14		T577	7
values[65]	92	1			T71	10		T500	21		T848	5
values[66]	124	1			T71	12		T500	15		T848	14
values[67]	87	1			T71	5		T500	9		T848	8
values[68]	76	1			T71	2		T500	6		T848	7
values[69]	64	1			T500	4		T848	2		T852	1
values[70]	84	1			T500	13		T848	3		T852	1
values[71]	66	1			T500	8		T848	5		T852	1
values[72]	81	1			T500	15		T848	6		T852	1
values[73]	75	1			T500	9		T848	4		T852	1
values[74]	68	1			T500	8		T848	6		T852	1
values[75]	56	1			T500	1		T848	4		T852	1
values[76]	58	1			T500	9		T848	6		T852	1
values[77]	96	1			T500	11		T848	14		T852	1
values[78]	59	1			T500	5		T852	1		T855	1
values[79]	49	1			T500	6		T852	1		T855	2
values[80]	49	1			T500	9		T852	1		T855	1
values[81]	58	1			T500	14		T852	1		T855	7
values[82]	38	1			T500	7		T852	1		T855	4
values[83]	40	1			T500	5		T852	1		T855	5
values[84]	39	1			T500	3		T852	1		T855	3
values[85]	45	1			T500	5		T852	1		T855	2
values[86]	44	1			T500	11		T852	1		T855	1
values[87]	40	1			T500	4		T852	1		T855	1
values[88]	42	1			T500	12		T852	1		T855	1
values[89]	44	1			T500	3		T852	2		T855	2
values[90]	48	1			T500	7		T852	1		T855	2
values[91]	44	1			T500	6		T852	2		T855	5
values[92]	45	1			T500	7		T852	2		T855	2
values[93]	51	1			T500	8		T852	2		T855	8
values[94]	44	1			T500	4		T852	4		T855	5
values[95]	44	1			T500	11		T852	1		T855	6
values[96]	54	1			T500	7		T852	1		T855	1
values[97]	49	1			T500	11		T852	5		T855	4
values[98]	44	1			T500	5		T852	1		T855	1
values[99]	43	1			T500	2		T852	1		T855	4
values[100]	51	1			T500	5		T852	1		T855	3
values[101]	77	1			T500	14		T852	1		T855	1
values[102]	69	1			T500	7		T852	4		T855	5
values[103]	44	1			T500	3		T852	1		T855	7
values[104]	53	1			T500	3		T852	2		T855	8
values[105]	43	1			T500	3		T852	2		T855	4
values[106]	59	1			T500	7		T852	7		T855	1
values[107]	33	1			T500	2		T852	3		T497	1
values[108]	47	1			T500	1		T852	2		T497	2
values[109]	53	1			T500	1		T852	3		T497	2
values[110]	40	1			T852	2		T497	2		T875	2
values[111]	34	1			T852	3		T497	1		T875	1
values[112]	37	1			T852	1		T497	1		T875	1
values[113]	42	1			T852	1		T497	1		T875	5
values[114]	29	1			T852	1		T497	1		T875	1
values[115]	43	1			T852	1		T497	1		T875	1
values[116]	43	1			T852	5		T497	6		T875	3
values[117]	29	1			T852	1		T497	1		T875	4
values[118]	42	1			T852	3		T497	3		T875	3
values[119]	47	1			T852	2		T497	3		T875	1
values[120]	42	1			T852	2		T497	3		T875	3
values[121]	38	1			T852	1		T497	2		T875	1
values[122]	47	1			T852	2		T497	4		T875	3
values[123]	39	1			T852	1		T497	1		T875	2
values[124]	52	1			T852	2		T497	5		T875	1
values[125]	37	1			T852	2		T497	2		T875	2
values[126]	79	1			T852	2		T497	2		T875	3
values[127]	689	1			T852	42		T497	23		T875	31
values[128]	6145	1			T852	382		T497	309		T875	341