Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	95.53	94.17	95.47		95.13	97.53	99.57

Total tests in report: 2882

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.72	39.72	44.94	44.94	42.99	42.99	32.73	32.73			58.03	58.03	59.27	59.27	0.38	0.38	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1967370869
50.33	10.61	52.73	7.79	59.36	16.37	36.88	4.15			69.16	11.13	82.34	23.08	1.54	1.16	/workspace/coverage/cover_reg_top/4.chip_csr_rw.2071467829
55.95	5.62	61.65	8.92	61.48	2.12	40.74	3.86			69.53	0.37	82.34	0.00	19.99	18.45	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1390979639
61.38	5.43	73.17	11.52	68.81	7.33	44.31	3.57			79.68	10.15	82.34	0.00	19.99	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1653152517
64.90	3.52	73.17	0.00	69.13	0.31	44.31	0.00			79.79	0.11	82.34	0.00	40.68	20.69	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3817591361
68.40	3.50	79.22	6.05	73.54	4.41	48.27	3.96			81.81	2.01	86.89	4.55	40.68	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.507002124
71.47	3.07	79.23	0.01	73.56	0.02	66.66	18.39			81.82	0.02	86.89	0.00	40.68	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3829212844
73.75	2.28	79.23	0.00	73.56	0.00	66.66	0.00			81.82	0.00	86.89	0.00	54.35	13.68	/workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3805829972
75.61	1.85	79.23	0.00	73.56	0.00	66.66	0.00			81.82	0.00	86.89	0.00	65.48	11.13	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1654011567
77.37	1.76	80.19	0.97	75.35	1.79	71.05	4.40			83.00	1.18	87.06	0.17	67.54	2.06	/workspace/coverage/default/1.chip_sw_alert_test.935743305
79.11	1.75	83.25	3.05	78.63	3.28	71.54	0.49			85.77	2.78	87.94	0.87	67.54	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3350780587
80.48	1.37	83.31	0.06	78.63	0.00	79.52	7.97			85.77	0.00	88.11	0.17	67.54	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3053508796
81.81	1.33	84.64	1.33	79.78	1.14	80.01	0.49			87.09	1.31	91.78	3.67	67.54	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2928812518
83.08	1.27	86.84	2.20	81.77	2.00	81.05	1.04			89.47	2.39	91.78	0.00	67.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1348436019
84.15	1.08	86.84	0.00	81.83	0.06	81.05	0.00			89.47	0.00	91.78	0.00	73.94	6.40	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1072370827
85.19	1.04	88.52	1.68	83.18	1.35	83.02	1.96			90.35	0.88	92.13	0.35	73.94	0.00	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1793081053
86.11	0.92	88.52	0.00	83.18	0.00	83.02	0.00			90.35	0.00	92.13	0.00	79.47	5.53	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3253089725
87.02	0.91	89.21	0.70	83.32	0.15	83.61	0.59			90.50	0.15	95.98	3.85	79.47	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3072872742
87.75	0.73	89.21	0.00	83.32	0.00	83.61	0.00			90.50	0.00	95.98	0.00	83.88	4.41	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3493312971
88.46	0.71	89.21	0.00	83.53	0.20	83.61	0.00			90.55	0.05	95.98	0.00	87.86	3.98	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.4134490635
89.13	0.68	89.91	0.70	84.90	1.37	84.31	0.70			91.80	1.25	95.98	0.00	87.90	0.04	/workspace/coverage/default/1.chip_jtag_csr_rw.1814489329
89.76	0.63	91.31	1.40	85.95	1.06	84.74	0.43			92.68	0.88	95.98	0.00	87.90	0.00	/workspace/coverage/default/1.chip_sw_gpio.865095488
90.24	0.48	91.35	0.05	86.06	0.11	85.11	0.37			92.69	0.01	95.98	0.00	90.22	2.33	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.811485543
90.70	0.46	91.35	0.00	86.15	0.08	85.11	0.00			92.69	0.00	95.98	0.00	92.93	2.70	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3364644031
91.15	0.44	91.37	0.01	88.39	2.24	85.11	0.00			92.69	0.00	95.98	0.00	93.34	0.41	/workspace/coverage/cover_reg_top/22.chip_tl_errors.1999838385
91.51	0.36	91.93	0.57	88.90	0.51	85.69	0.58			93.20	0.51	95.98	0.00	93.34	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1640755943
91.84	0.33	91.94	0.01	88.90	0.01	87.65	1.96			93.20	0.00	95.98	0.00	93.34	0.00	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1155178979
92.15	0.31	91.94	0.00	88.99	0.08	87.65	0.00			93.22	0.02	95.98	0.00	95.12	1.79	/workspace/coverage/cover_reg_top/74.xbar_access_same_device.1548153067
92.43	0.28	92.22	0.28	89.12	0.13	88.83	1.17			93.30	0.08	95.98	0.00	95.12	0.00	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2098742878
92.70	0.27	92.22	0.00	89.30	0.18	88.83	0.00			93.32	0.02	95.98	0.00	96.57	1.45	/workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3714974541
92.95	0.25	93.04	0.82	89.50	0.20	88.87	0.04			93.41	0.09	96.33	0.35	96.57	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.777649895
93.20	0.24	93.20	0.16	89.61	0.11	89.87	1.00			93.60	0.19	96.33	0.00	96.58	0.01	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3638080882
93.43	0.24	93.20	0.00	89.80	0.19	89.87	0.00			93.63	0.03	96.33	0.00	97.78	1.20	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.2585980290
93.63	0.19	93.20	0.00	89.80	0.00	91.03	1.16			93.63	0.00	96.33	0.00	97.78	0.00	/workspace/coverage/default/1.chip_sw_flash_init.3369540857
93.81	0.18	93.50	0.30	90.46	0.66	91.08	0.05			93.69	0.06	96.33	0.00	97.78	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.363318229
93.98	0.17	93.86	0.36	90.79	0.32	91.43	0.35			93.69	0.00	96.33	0.00	97.78	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3338728825
94.13	0.15	93.91	0.05	91.16	0.38	91.49	0.05			94.10	0.41	96.33	0.00	97.78	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2453059250
94.25	0.12	93.93	0.02	91.26	0.10	91.85	0.36			94.15	0.05	96.50	0.17	97.78	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4120630537
94.35	0.11	94.09	0.16	91.43	0.17	91.91	0.06			94.42	0.27	96.50	0.00	97.78	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2030925660
94.45	0.09	94.09	0.00	91.43	0.00	92.46	0.55			94.42	0.00	96.50	0.00	97.78	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.27961527
94.54	0.09	94.09	0.01	91.44	0.01	93.01	0.55			94.42	0.00	96.50	0.00	97.78	0.00	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3892562821
94.62	0.08	94.09	0.00	91.91	0.47	93.01	0.00			94.42	0.00	96.50	0.00	97.78	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1994148545
94.69	0.07	94.16	0.07	91.91	0.00	93.37	0.36			94.43	0.01	96.50	0.00	97.78	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.1025058184
94.76	0.07	94.31	0.14	91.95	0.05	93.37	0.01			94.48	0.06	96.68	0.17	97.79	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.4065101475
94.84	0.07	94.31	0.00	92.15	0.20	93.38	0.01			94.71	0.23	96.68	0.00	97.79	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2403994906
94.90	0.07	94.31	0.00	92.26	0.11	93.38	0.00			94.71	0.00	96.68	0.00	98.10	0.31	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3612432568
94.97	0.07	94.31	0.00	92.26	0.00	93.79	0.41			94.71	0.00	96.68	0.00	98.10	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3940174054
95.04	0.06	94.43	0.12	92.36	0.10	93.86	0.07			94.81	0.10	96.68	0.00	98.10	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2664720526
95.10	0.06	94.50	0.07	92.40	0.05	93.88	0.02			94.84	0.03	96.85	0.17	98.11	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1350454021
95.14	0.04	94.50	0.00	92.47	0.06	93.88	0.00			94.84	0.00	96.85	0.00	98.30	0.19	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2613015211
95.18	0.04	94.50	0.00	92.70	0.24	93.88	0.00			94.84	0.00	96.85	0.00	98.30	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.2503773243
95.21	0.04	94.50	0.00	92.70	0.00	94.10	0.22			94.84	0.00	96.85	0.00	98.30	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.664117344
95.25	0.04	94.50	0.01	92.71	0.01	94.10	0.01			94.85	0.01	97.03	0.17	98.31	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2017361009
95.29	0.04	94.50	0.01	92.72	0.01	94.11	0.01			94.86	0.01	97.20	0.17	98.32	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2252395505
95.32	0.04	94.51	0.01	92.74	0.01	94.11	0.00			94.86	0.01	97.38	0.17	98.33	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002544495
95.36	0.04	94.51	0.00	92.74	0.01	94.14	0.03			94.86	0.00	97.55	0.17	98.33	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.409655681
95.39	0.03	94.51	0.00	92.74	0.00	94.34	0.20			94.86	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2722517912
95.42	0.03	94.54	0.03	92.84	0.10	94.34	0.00			94.92	0.06	97.55	0.00	98.33	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1385416794
95.45	0.03	94.57	0.03	92.87	0.03	94.42	0.08			94.94	0.02	97.55	0.00	98.33	0.00	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2381582176
95.48	0.03	94.65	0.07	92.90	0.03	94.43	0.01			94.99	0.05	97.55	0.00	98.33	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2519033464
95.50	0.02	94.65	0.00	92.94	0.04	94.43	0.00			95.01	0.02	97.55	0.00	98.43	0.09	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2806978679
95.53	0.02	94.65	0.01	92.94	0.00	94.56	0.13			95.02	0.01	97.55	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2992766466
95.55	0.02	94.65	0.00	92.94	0.00	94.71	0.14			95.02	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3223968371
95.57	0.02	94.65	0.00	92.94	0.00	94.84	0.13			95.02	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/1.chip_sw_aes_enc.2639712620
95.59	0.02	94.71	0.06	92.99	0.05	94.84	0.00			95.03	0.02	97.55	0.00	98.43	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3202334990
95.61	0.02	94.74	0.03	92.99	0.00	94.92	0.09			95.03	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4106233640
95.63	0.02	94.74	0.00	93.10	0.11	94.92	0.00			95.03	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3430531681
95.65	0.02	94.74	0.00	93.13	0.03	94.92	0.00			95.05	0.02	97.55	0.00	98.48	0.06	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2415384509
95.66	0.02	94.77	0.03	93.18	0.05	94.94	0.02			95.07	0.02	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1145513768
95.68	0.02	94.77	0.00	93.29	0.11	94.94	0.00			95.07	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.101973462
95.70	0.02	94.77	0.01	93.37	0.08	94.94	0.01			95.07	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1756028307
95.71	0.02	94.77	0.00	93.41	0.04	94.94	0.00			95.07	0.00	97.55	0.00	98.54	0.06	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4241690685
95.73	0.02	94.78	0.01	93.43	0.03	95.00	0.06			95.07	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3497176999
95.74	0.01	94.78	0.00	93.43	0.00	95.07	0.07			95.07	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1148975318
95.75	0.01	94.79	0.02	93.47	0.04	95.09	0.01			95.07	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2599794931
95.76	0.01	94.79	0.00	93.48	0.01	95.09	0.00			95.07	0.00	97.55	0.00	98.60	0.06	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.623442364
95.77	0.01	94.83	0.03	93.50	0.02	95.09	0.00			95.07	0.01	97.55	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1285471188
95.78	0.01	94.84	0.01	93.52	0.01	95.11	0.02			95.08	0.01	97.55	0.00	98.61	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2983295245
95.79	0.01	94.84	0.00	93.58	0.06	95.11	0.00			95.08	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.698645019
95.80	0.01	94.84	0.00	93.63	0.05	95.11	0.00			95.08	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1361554494
95.81	0.01	94.84	0.00	93.66	0.03	95.11	0.00			95.08	0.00	97.55	0.00	98.64	0.02	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3774914312
95.82	0.01	94.86	0.02	93.66	0.01	95.11	0.01			95.10	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2836231831
95.83	0.01	94.88	0.02	93.67	0.01	95.11	0.01			95.11	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4037338814
95.84	0.01	94.88	0.00	93.70	0.02	95.11	0.00			95.11	0.00	97.55	0.00	98.66	0.02	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2978446638
95.84	0.01	94.88	0.00	93.74	0.05	95.11	0.00			95.11	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2084085949
95.85	0.01	94.88	0.00	93.74	0.00	95.15	0.04			95.11	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2491310126
95.86	0.01	94.88	0.00	93.76	0.01	95.15	0.00			95.11	0.00	97.55	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1312950101
95.86	0.01	94.88	0.00	93.76	0.00	95.19	0.04			95.11	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.670487943
95.87	0.01	94.88	0.00	93.79	0.04	95.19	0.00			95.11	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2895396233
95.88	0.01	94.88	0.00	93.79	0.00	95.19	0.00			95.11	0.00	97.55	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3366078983
95.88	0.01	94.88	0.00	93.82	0.03	95.19	0.00			95.11	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all.3290409088
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96.09	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.841911589
96.09	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/62.chip_sw_all_escalation_resets.962274016
96.09	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1856885643
96.09	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1154191131
96.10	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118169032
96.10	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.828252162
96.10	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982594264
96.10	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3056980687
96.10	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/9.chip_sw_all_escalation_resets.182295088
96.11	0.01	94.93	0.00	94.08	0.00	95.37	0.00			95.13	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4273377335
96.11	0.01	94.93	0.00	94.09	0.01	95.37	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.9405216
96.11	0.01	94.93	0.00	94.10	0.01	95.37	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.869149777
96.11	0.01	94.94	0.01	94.10	0.00	95.38	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/59.chip_sw_all_escalation_resets.2893475402
96.11	0.01	94.94	0.00	94.10	0.00	95.39	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2592282618
96.11	0.01	94.94	0.00	94.10	0.00	95.40	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2336497577
96.12	0.01	94.94	0.00	94.10	0.00	95.41	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.947665012
96.12	0.01	94.94	0.00	94.10	0.00	95.42	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1187381211
96.12	0.01	94.94	0.01	94.10	0.00	95.42	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.2531642068
96.12	0.01	94.94	0.00	94.11	0.01	95.42	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1322193177
96.12	0.01	94.94	0.00	94.12	0.01	95.42	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.3805894573
96.12	0.01	94.94	0.00	94.12	0.01	95.42	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2482511525
96.12	0.01	94.94	0.00	94.13	0.01	95.42	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4191567260
96.12	0.01	94.94	0.00	94.14	0.01	95.42	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.758302498
96.13	0.01	94.94	0.00	94.14	0.00	95.43	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.44697278
96.13	0.01	94.94	0.00	94.14	0.00	95.44	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2080854730
96.13	0.01	94.95	0.01	94.14	0.00	95.44	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2732593787
96.13	0.01	94.95	0.00	94.14	0.00	95.44	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.548251223
96.13	0.01	94.95	0.00	94.14	0.00	95.45	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.32134886
96.13	0.01	94.95	0.00	94.14	0.00	95.45	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2987731281
96.13	0.01	94.95	0.00	94.14	0.00	95.46	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4224430941
96.13	0.01	94.95	0.00	94.14	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all.2717254391
96.13	0.01	94.95	0.00	94.14	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2346883041
96.13	0.01	94.95	0.00	94.15	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.4206348342
96.13	0.01	94.95	0.00	94.15	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.616256761
96.13	0.01	94.95	0.00	94.16	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4140877733
96.14	0.01	94.95	0.00	94.16	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4023117561
96.14	0.01	94.95	0.00	94.16	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2758562248
96.14	0.01	94.95	0.00	94.17	0.01	95.46	0.00			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.692698897
96.14	0.01	94.95	0.00	94.17	0.00	95.46	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1416636196
96.14	0.01	94.95	0.00	94.17	0.00	95.46	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2574878175
96.14	0.01	94.95	0.00	94.17	0.00	95.46	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3609068799
96.14	0.01	94.95	0.00	94.17	0.00	95.47	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1802039309
96.14	0.01	94.95	0.00	94.17	0.00	95.47	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2083607268
96.14	0.01	94.95	0.00	94.17	0.00	95.47	0.01			95.13	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.903335604

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1039649334
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2152251802
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1385507565
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1460617591
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2518323207
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3629938333
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2261584454
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2586809240
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1839069345
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1726534297
/workspace/coverage/cover_reg_top/0.xbar_error_random.2285060430
/workspace/coverage/cover_reg_top/0.xbar_random.3746708208
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.410347294
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1136347558
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.327836775
/workspace/coverage/cover_reg_top/0.xbar_same_source.2797221223
/workspace/coverage/cover_reg_top/0.xbar_smoke.3028448448
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1887857195
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2869216109
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3905948783
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3436852985
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.430935898
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1157557708
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2135420234
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3718109193
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.342507250
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2475875204
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2692320385
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.336891857
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4266499573
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3457442643
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3942277563
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.53461001
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1114223284
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3493074880
/workspace/coverage/cover_reg_top/1.xbar_error_random.2677623350
/workspace/coverage/cover_reg_top/1.xbar_random.3691746128
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2720715287
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3643948202
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3736786907
/workspace/coverage/cover_reg_top/1.xbar_same_source.97203531
/workspace/coverage/cover_reg_top/1.xbar_smoke.3915763826
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.744696130
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2542175515
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2690601917
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2646560641
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.226045366
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.194219802
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3185922044
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2651038271
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1034986502
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.349464483
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1409618041
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2545936554
/workspace/coverage/cover_reg_top/10.xbar_error_random.4151134311
/workspace/coverage/cover_reg_top/10.xbar_random.2138996803
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1432313681
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3562288653
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.832159056
/workspace/coverage/cover_reg_top/10.xbar_same_source.1522088581
/workspace/coverage/cover_reg_top/10.xbar_smoke.2670224969
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2129733334
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.990034819
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2122295549
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.478014482
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1155884973
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2856226016
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3593185326
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2055487580
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.196672368
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1968855580
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2336714708
/workspace/coverage/cover_reg_top/11.xbar_error_random.2744012291
/workspace/coverage/cover_reg_top/11.xbar_random.1759857818
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3694513462
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2544377603
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2842221421
/workspace/coverage/cover_reg_top/11.xbar_same_source.4216425995
/workspace/coverage/cover_reg_top/11.xbar_smoke.631436750
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4192953725
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2525145569
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.768348382
/workspace/coverage/cover_reg_top/11.xbar_stress_all.61791020
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2852303156
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2140283337
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4165729074
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2208918613
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2110368687
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2261086318
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.618388594
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1216235770
/workspace/coverage/cover_reg_top/12.xbar_error_random.650020722
/workspace/coverage/cover_reg_top/12.xbar_random.3552318341
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4156919773
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3030944352
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2892000463
/workspace/coverage/cover_reg_top/12.xbar_same_source.516183039
/workspace/coverage/cover_reg_top/12.xbar_smoke.3600875230
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1182158350
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4229595156
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.298401980
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2629461172
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.691631495
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.83685738
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1418477114
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2696989891
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2909838985
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3196499633
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1728347391
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2337151510
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.482083633
/workspace/coverage/cover_reg_top/13.xbar_error_random.234658892
/workspace/coverage/cover_reg_top/13.xbar_random.2246041492
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3826178197
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.113781943
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2468659864
/workspace/coverage/cover_reg_top/13.xbar_same_source.1508414021
/workspace/coverage/cover_reg_top/13.xbar_smoke.637332741
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.157125291
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.4067307150
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1520946410
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3418023331
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4247221459
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1416734112
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1192748041
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1275644410
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2120642140
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3471392091
/workspace/coverage/cover_reg_top/14.chip_tl_errors.2276010115
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2154892383
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3700363009
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2796089383
/workspace/coverage/cover_reg_top/14.xbar_error_random.2493500679
/workspace/coverage/cover_reg_top/14.xbar_random.526048031
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.79760193
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1411517027
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1468221926
/workspace/coverage/cover_reg_top/14.xbar_same_source.817669265
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/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.783626711
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.306319944
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1119396396
/workspace/coverage/default/2.rom_e2e_smoke.1014710416
/workspace/coverage/default/2.rom_e2e_static_critical.1217354549
/workspace/coverage/default/2.rom_keymgr_functest.1981183193
/workspace/coverage/default/2.rom_volatile_raw_unlock.1220820237
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/workspace/coverage/default/26.chip_sw_all_escalation_resets.2770000037
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588080640
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1980230045
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.491994942
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1917991305
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.3168137584
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.937885045
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.375122105
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3251355464
/workspace/coverage/default/32.chip_sw_all_escalation_resets.843298918
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1301984200
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1887831050
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2360162071
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078029048
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056186988
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050254851
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.362371457
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1792312694
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.817416814
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.185252055
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.676085397
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2417909681
/workspace/coverage/default/4.chip_sw_uart_tx_rx.838736692
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.931377270
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.966648644
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1606442839
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1567244621
/workspace/coverage/default/4.chip_tap_straps_dev.1659472855
/workspace/coverage/default/4.chip_tap_straps_prod.2458681303
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3862777899
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426074869
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1388145931
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3099275490
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2402023033
/workspace/coverage/default/43.chip_sw_all_escalation_resets.4213021947
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965812430
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.16803027
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3929904019
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3770902201
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1947056762
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3781743401
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797429567
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2113120223
/workspace/coverage/default/5.chip_sw_all_escalation_resets.197199633
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.117294025
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4048434226
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.433637397
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1071429804
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734008785
/workspace/coverage/default/50.chip_sw_all_escalation_resets.198507163
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3701207406
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399559484
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2716969236
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3822909254
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593791923
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2600847576
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2512384598
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1869941676
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779307468
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1911579033
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3972989642
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2290669705
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.989699059
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.94527070
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3256260851
/workspace/coverage/default/60.chip_sw_all_escalation_resets.148507752
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.698969877
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1909012696
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1438455082
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330678207
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2194073749
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2716253757
/workspace/coverage/default/64.chip_sw_all_escalation_resets.462264664
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959006135
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2855747933
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3347428245
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3403417788
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.989088190
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.755737267
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3748133657
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.773043579
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3567969089
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3570694684
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1905182111
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.563637324
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.70599103
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1767097501
/workspace/coverage/default/70.chip_sw_all_escalation_resets.4291037514
/workspace/coverage/default/71.chip_sw_all_escalation_resets.4275921573
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3166031192
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1967197796
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119656700
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2637857472
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001947310
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3735822133
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4108743590
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3346171568
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.222023550
/workspace/coverage/default/76.chip_sw_all_escalation_resets.689082409
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3117342423
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1528152401
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3652591467
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1271417590
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2515260215
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4067870584
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2037909566
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.235175809
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3421460725
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3145385797
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.813647103
/workspace/coverage/default/80.chip_sw_all_escalation_resets.878294883
/workspace/coverage/default/81.chip_sw_all_escalation_resets.445084569
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2004707538
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3425005324
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827758591
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2043570555
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3529836022
/workspace/coverage/default/84.chip_sw_all_escalation_resets.742077602
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982672620
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2146315705
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763501695
/workspace/coverage/default/86.chip_sw_all_escalation_resets.691024171
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319230482
/workspace/coverage/default/87.chip_sw_all_escalation_resets.508494012
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196202501
/workspace/coverage/default/88.chip_sw_all_escalation_resets.956638913
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.598524828
/workspace/coverage/default/89.chip_sw_all_escalation_resets.4274678252
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1814948180
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.722849876
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4292225072
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3123822389
/workspace/coverage/default/92.chip_sw_all_escalation_resets.4081456634
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4128635685
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1034393469
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2207186260
/workspace/coverage/default/96.chip_sw_all_escalation_resets.250779818
/workspace/coverage/default/97.chip_sw_all_escalation_resets.393219507
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3159718362
/workspace/coverage/default/99.chip_sw_all_escalation_resets.31274586
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.587047245
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3676098104
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3888883063
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3948511355
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4242834143
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2449375178
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1602427009
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2027880926

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Total test records in report: 2882

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1526375128			Jun 23 08:08:23 PM PDT 24	Jun 23 08:34:08 PM PDT 24	14274652707 ps
T5	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2983295245			Jun 23 08:18:53 PM PDT 24	Jun 23 08:27:56 PM PDT 24	5038122236 ps
T6	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3400755833			Jun 23 08:08:21 PM PDT 24	Jun 23 08:10:09 PM PDT 24	2250959123 ps
T18	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1240213420			Jun 23 07:56:28 PM PDT 24	Jun 23 08:00:17 PM PDT 24	3136854400 ps
T19	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1230851247			Jun 23 07:50:52 PM PDT 24	Jun 23 07:56:01 PM PDT 24	3377737114 ps
T45	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3829212844			Jun 23 07:52:09 PM PDT 24	Jun 23 08:16:42 PM PDT 24	6208484472 ps
T62	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1967370869			Jun 23 07:49:50 PM PDT 24	Jun 23 08:19:32 PM PDT 24	13571422731 ps
T20	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3940174054			Jun 23 07:56:05 PM PDT 24	Jun 23 08:05:40 PM PDT 24	5395106098 ps
T82	/workspace/coverage/default/43.chip_sw_all_escalation_resets.4213021947			Jun 23 08:21:43 PM PDT 24	Jun 23 08:31:57 PM PDT 24	5466788800 ps
T83	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3213095723			Jun 23 08:13:41 PM PDT 24	Jun 23 08:20:40 PM PDT 24	4197570000 ps
T58	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3104754838			Jun 23 07:50:52 PM PDT 24	Jun 23 08:01:36 PM PDT 24	4484333736 ps
T171	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3072872742			Jun 23 08:13:12 PM PDT 24	Jun 23 08:18:43 PM PDT 24	3006240270 ps
T124	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4067870584			Jun 23 08:19:34 PM PDT 24	Jun 23 08:27:49 PM PDT 24	4099959920 ps
T164	/workspace/coverage/default/0.chip_sival_flash_info_access.3978166800			Jun 23 07:49:13 PM PDT 24	Jun 23 07:55:22 PM PDT 24	3090669330 ps
T78	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2098742878			Jun 23 07:58:34 PM PDT 24	Jun 23 08:19:25 PM PDT 24	10458867080 ps
T296	/workspace/coverage/default/0.chip_plic_all_irqs_20.1653152517			Jun 23 07:51:25 PM PDT 24	Jun 23 08:03:54 PM PDT 24	4676722524 ps
T187	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3025812839			Jun 23 07:52:16 PM PDT 24	Jun 23 07:58:26 PM PDT 24	5698795036 ps
T29	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2381582176			Jun 23 08:21:22 PM PDT 24	Jun 23 08:30:09 PM PDT 24	4337011592 ps
T110	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.137913130			Jun 23 07:54:35 PM PDT 24	Jun 23 08:09:59 PM PDT 24	5527545906 ps
T297	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336354325			Jun 23 08:22:22 PM PDT 24	Jun 23 08:28:56 PM PDT 24	4196417200 ps
T32	/workspace/coverage/default/0.chip_sw_usbdev_pullup.59046225			Jun 23 07:53:07 PM PDT 24	Jun 23 07:57:21 PM PDT 24	2510269134 ps
T174	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1309779580			Jun 23 07:51:06 PM PDT 24	Jun 23 07:58:59 PM PDT 24	4026813944 ps
T111	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2611150418			Jun 23 07:51:24 PM PDT 24	Jun 23 07:55:21 PM PDT 24	2794846387 ps
T120	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1689053142			Jun 23 07:52:32 PM PDT 24	Jun 23 08:08:10 PM PDT 24	9484926298 ps
T209	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.94527070			Jun 23 08:18:31 PM PDT 24	Jun 23 08:27:33 PM PDT 24	3386437132 ps
T145	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2599794931			Jun 23 08:18:28 PM PDT 24	Jun 23 08:28:59 PM PDT 24	4257539052 ps
T54	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1793081053			Jun 23 08:19:51 PM PDT 24	Jun 23 09:11:49 PM PDT 24	15277169376 ps
T117	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3816266990			Jun 23 08:06:16 PM PDT 24	Jun 23 08:39:48 PM PDT 24	12909920356 ps
T284	/workspace/coverage/default/0.chip_sw_hmac_enc.2589004746			Jun 23 07:50:31 PM PDT 24	Jun 23 07:54:44 PM PDT 24	2961619924 ps
T285	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2654657525			Jun 23 07:54:06 PM PDT 24	Jun 23 08:14:09 PM PDT 24	6037120852 ps
T122	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3795282720			Jun 23 08:00:42 PM PDT 24	Jun 23 08:25:49 PM PDT 24	6186450386 ps
T21	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3223968371			Jun 23 08:07:43 PM PDT 24	Jun 23 08:09:54 PM PDT 24	2575888078 ps
T911	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1192520752			Jun 23 08:14:53 PM PDT 24	Jun 23 08:34:11 PM PDT 24	7605554645 ps
T912	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3431365939			Jun 23 07:53:13 PM PDT 24	Jun 23 07:56:14 PM PDT 24	2888525410 ps
T692	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3291648683			Jun 23 08:21:50 PM PDT 24	Jun 23 08:27:31 PM PDT 24	3240904404 ps
T691	/workspace/coverage/default/1.chip_sw_csrng_kat_test.2948419884			Jun 23 07:59:53 PM PDT 24	Jun 23 08:03:59 PM PDT 24	2779057790 ps
T22	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3638080882			Jun 23 07:55:06 PM PDT 24	Jun 23 10:52:40 PM PDT 24	58747480000 ps
T245	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4023117561			Jun 23 07:51:51 PM PDT 24	Jun 23 08:07:50 PM PDT 24	4749335764 ps
T121	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3569693352			Jun 23 08:14:21 PM PDT 24	Jun 23 08:20:31 PM PDT 24	6133285520 ps
T112	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4120630537			Jun 23 07:52:06 PM PDT 24	Jun 23 07:59:48 PM PDT 24	4017377811 ps
T210	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1446154479			Jun 23 07:54:08 PM PDT 24	Jun 23 08:06:40 PM PDT 24	4528359640 ps
T365	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.286464974			Jun 23 07:56:34 PM PDT 24	Jun 23 08:09:14 PM PDT 24	7791563930 ps
T366	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.123089471			Jun 23 08:13:04 PM PDT 24	Jun 23 08:17:53 PM PDT 24	3291938360 ps
T343	/workspace/coverage/default/99.chip_sw_all_escalation_resets.31274586			Jun 23 08:25:44 PM PDT 24	Jun 23 08:32:43 PM PDT 24	4834504536 ps
T108	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2407551616			Jun 23 07:53:09 PM PDT 24	Jun 23 09:00:02 PM PDT 24	24852689530 ps
T367	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.680088824			Jun 23 08:22:16 PM PDT 24	Jun 23 08:29:19 PM PDT 24	3299637490 ps
T166	/workspace/coverage/default/1.chip_sw_flash_init.3369540857			Jun 23 07:53:16 PM PDT 24	Jun 23 08:28:47 PM PDT 24	22127273774 ps
T57	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2651594479			Jun 23 08:14:03 PM PDT 24	Jun 23 08:25:15 PM PDT 24	4480819249 ps
T248	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1905182111			Jun 23 08:17:43 PM PDT 24	Jun 23 09:53:37 PM PDT 24	23582296974 ps
T421	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3456302207			Jun 23 08:01:16 PM PDT 24	Jun 23 08:05:44 PM PDT 24	2731345864 ps
T396	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1023854295			Jun 23 08:21:36 PM PDT 24	Jun 23 08:29:36 PM PDT 24	4909545008 ps
T67	/workspace/coverage/default/0.chip_tap_straps_testunlock0.4100032995			Jun 23 07:52:38 PM PDT 24	Jun 23 08:00:30 PM PDT 24	4905189309 ps
T249	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1155178979			Jun 23 08:19:34 PM PDT 24	Jun 23 08:55:57 PM PDT 24	11060336824 ps
T152	/workspace/coverage/default/0.chip_plic_all_irqs_10.1640755943			Jun 23 07:52:32 PM PDT 24	Jun 23 08:01:45 PM PDT 24	3616661568 ps
T506	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2938707338			Jun 23 08:06:13 PM PDT 24	Jun 23 08:09:48 PM PDT 24	2578127020 ps
T170	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3380008943			Jun 23 08:00:59 PM PDT 24	Jun 23 08:10:34 PM PDT 24	5144802120 ps
T55	/workspace/coverage/default/2.rom_e2e_smoke.1014710416			Jun 23 08:20:36 PM PDT 24	Jun 23 09:21:34 PM PDT 24	15818869432 ps
T217	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2365133938			Jun 23 08:19:37 PM PDT 24	Jun 23 08:31:54 PM PDT 24	5660672440 ps
T913	/workspace/coverage/default/2.chip_sw_csrng_smoketest.3416099698			Jun 23 08:15:06 PM PDT 24	Jun 23 08:19:49 PM PDT 24	2804103380 ps
T337	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3403417788			Jun 23 08:23:42 PM PDT 24	Jun 23 08:33:14 PM PDT 24	6191592416 ps
T239	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2262781256			Jun 23 07:53:10 PM PDT 24	Jun 23 08:24:25 PM PDT 24	11486254920 ps
T709	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196202501			Jun 23 08:26:08 PM PDT 24	Jun 23 08:30:43 PM PDT 24	3597915316 ps
T73	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3805615145			Jun 23 07:54:10 PM PDT 24	Jun 23 08:51:21 PM PDT 24	30688853937 ps
T23	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3350780587			Jun 23 08:06:20 PM PDT 24	Jun 23 08:12:44 PM PDT 24	3821851202 ps
T30	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4189793974			Jun 23 07:50:17 PM PDT 24	Jun 23 11:26:29 PM PDT 24	77528733433 ps
T118	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1195016461			Jun 23 08:12:34 PM PDT 24	Jun 23 08:24:55 PM PDT 24	4956695250 ps
T250	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2290669705			Jun 23 08:18:25 PM PDT 24	Jun 23 09:00:52 PM PDT 24	13167851128 ps
T726	/workspace/coverage/default/1.chip_sw_aes_enc.2639712620			Jun 23 07:58:00 PM PDT 24	Jun 23 08:03:03 PM PDT 24	3261978196 ps
T331	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3925463100			Jun 23 07:56:20 PM PDT 24	Jun 23 08:07:42 PM PDT 24	4365587782 ps
T63	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2289991546			Jun 23 08:08:21 PM PDT 24	Jun 23 10:58:43 PM PDT 24	57652618122 ps
T687	/workspace/coverage/default/2.chip_sw_aes_masking_off.1579171807			Jun 23 08:10:54 PM PDT 24	Jun 23 08:17:50 PM PDT 24	2643808668 ps
T326	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.9405216			Jun 23 07:55:00 PM PDT 24	Jun 23 08:02:00 PM PDT 24	3733003208 ps
T206	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4172496908			Jun 23 08:06:39 PM PDT 24	Jun 23 08:22:05 PM PDT 24	5214445220 ps
T688	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2037909566			Jun 23 08:17:49 PM PDT 24	Jun 23 08:28:10 PM PDT 24	4143816216 ps
T149	/workspace/coverage/default/0.chip_sw_otbn_smoketest.1907950417			Jun 23 07:56:47 PM PDT 24	Jun 23 08:19:59 PM PDT 24	6348623380 ps
T914	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1865830492			Jun 23 07:54:57 PM PDT 24	Jun 23 07:58:09 PM PDT 24	2867390060 ps
T218	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1350454021			Jun 23 07:54:23 PM PDT 24	Jun 23 08:05:05 PM PDT 24	5889620994 ps
T115	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3442978856			Jun 23 07:49:16 PM PDT 24	Jun 23 07:51:31 PM PDT 24	2807061638 ps
T258	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2241481281			Jun 23 08:22:40 PM PDT 24	Jun 23 08:28:54 PM PDT 24	4121250000 ps
T186	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.204532030			Jun 23 08:10:57 PM PDT 24	Jun 23 08:19:06 PM PDT 24	5517353432 ps
T259	/workspace/coverage/default/1.chip_sw_aes_idle.3239508889			Jun 23 07:59:49 PM PDT 24	Jun 23 08:03:50 PM PDT 24	2391415044 ps
T31	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3144110438			Jun 23 08:07:23 PM PDT 24	Jun 23 08:20:06 PM PDT 24	3849504851 ps
T59	/workspace/coverage/default/1.chip_sw_alert_test.935743305			Jun 23 07:58:17 PM PDT 24	Jun 23 08:02:57 PM PDT 24	3166056700 ps
T116	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1435706350			Jun 23 07:49:14 PM PDT 24	Jun 23 07:51:15 PM PDT 24	2753180852 ps
T207	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.227976469			Jun 23 07:54:26 PM PDT 24	Jun 23 08:08:45 PM PDT 24	5773374720 ps
T205	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1638487510			Jun 23 07:58:59 PM PDT 24	Jun 23 08:29:56 PM PDT 24	8158474602 ps
T344	/workspace/coverage/default/96.chip_sw_all_escalation_resets.250779818			Jun 23 08:26:24 PM PDT 24	Jun 23 08:36:00 PM PDT 24	4528257688 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2789550749			Jun 23 08:03:31 PM PDT 24	Jun 23 08:11:30 PM PDT 24	7668471310 ps
T97	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.463986519			Jun 23 08:12:43 PM PDT 24	Jun 23 08:19:52 PM PDT 24	4276879460 ps
T98	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.433637397			Jun 23 08:18:10 PM PDT 24	Jun 23 08:25:50 PM PDT 24	5894299875 ps
T99	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1615390658			Jun 23 07:51:56 PM PDT 24	Jun 23 07:57:07 PM PDT 24	3684998430 ps
T100	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3497176999			Jun 23 07:54:57 PM PDT 24	Jun 23 08:04:39 PM PDT 24	4303752874 ps
T101	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2074681230			Jun 23 08:21:46 PM PDT 24	Jun 23 08:32:42 PM PDT 24	5334318656 ps
T102	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.664117344			Jun 23 08:11:03 PM PDT 24	Jun 23 08:21:17 PM PDT 24	5559798687 ps
T68	/workspace/coverage/default/1.chip_tap_straps_rma.2555201812			Jun 23 08:02:16 PM PDT 24	Jun 23 08:19:19 PM PDT 24	9010383150 ps
T103	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.733588535			Jun 23 08:01:36 PM PDT 24	Jun 23 08:08:29 PM PDT 24	4254421048 ps
T104	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3338728825			Jun 23 07:54:19 PM PDT 24	Jun 23 08:02:22 PM PDT 24	5280392750 ps
T163	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3053508796			Jun 23 07:57:24 PM PDT 24	Jun 23 08:41:40 PM PDT 24	34092636088 ps
T246	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2066483852			Jun 23 07:56:30 PM PDT 24	Jun 23 08:41:23 PM PDT 24	32384409905 ps
T380	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.384784061			Jun 23 08:00:33 PM PDT 24	Jun 23 08:04:44 PM PDT 24	2856144550 ps
T431	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1890449882			Jun 23 07:57:09 PM PDT 24	Jun 23 08:08:12 PM PDT 24	5151806619 ps
T329	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1602644174			Jun 23 07:56:30 PM PDT 24	Jun 23 08:07:52 PM PDT 24	3884174850 ps
T711	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.94757292			Jun 23 07:57:35 PM PDT 24	Jun 23 08:04:45 PM PDT 24	3870948956 ps
T690	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470156751			Jun 23 08:18:46 PM PDT 24	Jun 23 08:25:51 PM PDT 24	4078171920 ps
T2	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2928812518			Jun 23 08:02:17 PM PDT 24	Jun 23 08:24:36 PM PDT 24	18920686426 ps
T56	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4208199379			Jun 23 08:16:14 PM PDT 24	Jun 23 09:16:27 PM PDT 24	11990377064 ps
T172	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2651794147			Jun 23 08:03:40 PM PDT 24	Jun 23 08:08:57 PM PDT 24	2895308463 ps
T310	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2202105720			Jun 23 07:57:06 PM PDT 24	Jun 23 08:14:38 PM PDT 24	11072683171 ps
T710	/workspace/coverage/default/15.chip_sw_all_escalation_resets.636637358			Jun 23 08:19:05 PM PDT 24	Jun 23 08:30:00 PM PDT 24	6161325500 ps
T60	/workspace/coverage/default/0.chip_sw_alert_test.4082032729			Jun 23 07:50:21 PM PDT 24	Jun 23 07:54:11 PM PDT 24	2401457510 ps
T3	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1882774745			Jun 23 07:55:04 PM PDT 24	Jun 23 08:02:38 PM PDT 24	7530170880 ps
T147	/workspace/coverage/default/2.chip_sw_power_sleep_load.3472829078			Jun 23 08:15:42 PM PDT 24	Jun 23 08:23:54 PM PDT 24	9446751296 ps
T333	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.569569111			Jun 23 08:15:14 PM PDT 24	Jun 23 08:18:59 PM PDT 24	2891269279 ps
T311	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1796577835			Jun 23 07:57:48 PM PDT 24	Jun 23 08:22:16 PM PDT 24	12860143308 ps
T195	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1404319041			Jun 23 08:08:19 PM PDT 24	Jun 23 11:40:36 PM PDT 24	78918710838 ps
T362	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3028737545			Jun 23 08:00:48 PM PDT 24	Jun 23 09:12:51 PM PDT 24	16023608560 ps
T35	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3170787532			Jun 23 07:50:25 PM PDT 24	Jun 23 07:57:31 PM PDT 24	3489463094 ps
T167	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1263603727			Jun 23 08:13:56 PM PDT 24	Jun 23 08:40:01 PM PDT 24	18079278807 ps
T915	/workspace/coverage/default/2.chip_sw_kmac_idle.1979739065			Jun 23 08:11:24 PM PDT 24	Jun 23 08:15:39 PM PDT 24	2887167344 ps
T916	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2190482567			Jun 23 07:56:09 PM PDT 24	Jun 23 08:10:09 PM PDT 24	4403359316 ps
T813	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3652646537			Jun 23 08:21:56 PM PDT 24	Jun 23 08:27:33 PM PDT 24	3824927968 ps
T381	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.740405983			Jun 23 08:08:34 PM PDT 24	Jun 23 08:13:14 PM PDT 24	3186952280 ps
T153	/workspace/coverage/default/2.chip_plic_all_irqs_10.4250801672			Jun 23 08:12:26 PM PDT 24	Jun 23 08:22:08 PM PDT 24	4438778150 ps
T917	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3284870601			Jun 23 08:14:02 PM PDT 24	Jun 23 08:21:42 PM PDT 24	3702357440 ps
T918	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.465363227			Jun 23 08:14:30 PM PDT 24	Jun 23 08:18:56 PM PDT 24	3038373553 ps
T342	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1470423296			Jun 23 08:18:59 PM PDT 24	Jun 23 08:44:00 PM PDT 24	8228603750 ps
T814	/workspace/coverage/default/6.chip_sw_all_escalation_resets.3972989642			Jun 23 08:18:19 PM PDT 24	Jun 23 08:27:37 PM PDT 24	5245435332 ps
T79	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1183501277			Jun 23 07:49:56 PM PDT 24	Jun 23 08:10:00 PM PDT 24	10409218400 ps
T708	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1447384169			Jun 23 08:22:30 PM PDT 24	Jun 23 08:31:45 PM PDT 24	4391536728 ps
T119	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3895410047			Jun 23 08:03:11 PM PDT 24	Jun 23 08:16:59 PM PDT 24	4797452546 ps
T919	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2929776685			Jun 23 08:06:10 PM PDT 24	Jun 23 08:18:57 PM PDT 24	4149679476 ps
T397	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2813503374			Jun 23 07:52:08 PM PDT 24	Jun 23 07:56:36 PM PDT 24	3030596082 ps
T198	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1628442142			Jun 23 08:13:34 PM PDT 24	Jun 23 08:19:30 PM PDT 24	3324562695 ps
T208	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1510950629			Jun 23 07:49:05 PM PDT 24	Jun 23 08:02:51 PM PDT 24	4187263208 ps
T222	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4013690201			Jun 23 08:11:00 PM PDT 24	Jun 23 08:33:59 PM PDT 24	6747933376 ps
T920	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.253982950			Jun 23 07:49:27 PM PDT 24	Jun 23 08:06:56 PM PDT 24	5641326242 ps
T125	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2667180823			Jun 23 08:11:23 PM PDT 24	Jun 23 08:19:32 PM PDT 24	4837979360 ps
T921	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3696944828			Jun 23 07:51:41 PM PDT 24	Jun 23 08:00:04 PM PDT 24	4567152856 ps
T169	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3650171821			Jun 23 07:49:11 PM PDT 24	Jun 23 07:51:20 PM PDT 24	2320854133 ps
T764	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2207186260			Jun 23 08:25:57 PM PDT 24	Jun 23 08:37:17 PM PDT 24	5625720384 ps
T922	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.879603464			Jun 23 08:12:48 PM PDT 24	Jun 23 08:28:50 PM PDT 24	8094973522 ps
T336	/workspace/coverage/default/64.chip_sw_all_escalation_resets.462264664			Jun 23 08:22:30 PM PDT 24	Jun 23 08:31:03 PM PDT 24	5336011000 ps
T923	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1370032592			Jun 23 07:50:48 PM PDT 24	Jun 23 07:55:28 PM PDT 24	3171835618 ps
T924	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.609166923			Jun 23 07:50:47 PM PDT 24	Jun 23 07:59:59 PM PDT 24	4039034316 ps
T165	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.672470451			Jun 23 08:07:59 PM PDT 24	Jun 23 08:38:45 PM PDT 24	22816823770 ps
T925	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.575842500			Jun 23 07:48:19 PM PDT 24	Jun 23 08:05:49 PM PDT 24	5016552400 ps
T46	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.777649895			Jun 23 08:06:53 PM PDT 24	Jun 23 08:10:42 PM PDT 24	2472039346 ps
T926	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1397435260			Jun 23 07:55:29 PM PDT 24	Jun 23 07:59:17 PM PDT 24	2731939100 ps
T927	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2121403960			Jun 23 08:10:16 PM PDT 24	Jun 23 08:16:55 PM PDT 24	5327127528 ps
T148	/workspace/coverage/default/0.chip_sw_power_idle_load.2531642068			Jun 23 07:55:19 PM PDT 24	Jun 23 08:06:00 PM PDT 24	4929828192 ps
T212	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3544015537			Jun 23 07:53:06 PM PDT 24	Jun 23 08:03:30 PM PDT 24	3723006304 ps
T779	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3570694684			Jun 23 08:18:52 PM PDT 24	Jun 23 08:29:33 PM PDT 24	4931681006 ps
T734	/workspace/coverage/default/86.chip_sw_all_escalation_resets.691024171			Jun 23 08:26:13 PM PDT 24	Jun 23 08:38:26 PM PDT 24	6099990480 ps
T928	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2775963545			Jun 23 08:02:19 PM PDT 24	Jun 23 08:13:57 PM PDT 24	4565544528 ps
T741	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3652591467			Jun 23 08:25:18 PM PDT 24	Jun 23 08:31:45 PM PDT 24	3629668292 ps
T696	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1119396396			Jun 23 08:20:51 PM PDT 24	Jun 23 09:16:14 PM PDT 24	15238348296 ps
T929	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.125162312			Jun 23 08:04:00 PM PDT 24	Jun 23 08:07:42 PM PDT 24	2803155161 ps
T168	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.139034753			Jun 23 07:49:22 PM PDT 24	Jun 23 09:23:19 PM PDT 24	51131218085 ps
T221	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1804724467			Jun 23 07:57:37 PM PDT 24	Jun 23 08:17:17 PM PDT 24	7125365558 ps
T930	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.455756348			Jun 23 08:12:35 PM PDT 24	Jun 23 08:26:49 PM PDT 24	12147892906 ps
T733	/workspace/coverage/default/2.chip_sw_aon_timer_irq.696195875			Jun 23 08:08:17 PM PDT 24	Jun 23 08:14:55 PM PDT 24	3992860780 ps
T160	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3892562821			Jun 23 08:21:26 PM PDT 24	Jun 23 08:30:11 PM PDT 24	5123156204 ps
T838	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2971240476			Jun 23 08:20:23 PM PDT 24	Jun 23 08:34:18 PM PDT 24	4828900028 ps
T931	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.144734071			Jun 23 07:52:19 PM PDT 24	Jun 23 08:03:32 PM PDT 24	4560458744 ps
T505	/workspace/coverage/default/98.chip_sw_all_escalation_resets.3159718362			Jun 23 08:25:45 PM PDT 24	Jun 23 08:37:11 PM PDT 24	5671603168 ps
T146	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2057581421			Jun 23 08:16:48 PM PDT 24	Jun 23 08:30:40 PM PDT 24	4556576452 ps
T932	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2246380478			Jun 23 08:12:36 PM PDT 24	Jun 23 08:24:20 PM PDT 24	4424164396 ps
T933	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1516147291			Jun 23 08:01:27 PM PDT 24	Jun 23 08:10:41 PM PDT 24	5269020488 ps
T346	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2600847576			Jun 23 08:27:05 PM PDT 24	Jun 23 08:37:02 PM PDT 24	5594710760 ps
T934	/workspace/coverage/default/1.chip_sw_aes_smoketest.2420789833			Jun 23 08:05:54 PM PDT 24	Jun 23 08:09:25 PM PDT 24	2821907934 ps
T159	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1187381211			Jun 23 08:08:24 PM PDT 24	Jun 23 08:11:11 PM PDT 24	2493458804 ps
T935	/workspace/coverage/default/2.chip_sw_aes_enc.1559509882			Jun 23 08:10:19 PM PDT 24	Jun 23 08:13:33 PM PDT 24	2065584484 ps
T219	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2394261349			Jun 23 07:56:02 PM PDT 24	Jun 23 08:15:41 PM PDT 24	8398925882 ps
T840	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.813647103			Jun 23 08:25:08 PM PDT 24	Jun 23 08:31:31 PM PDT 24	3892763360 ps
T936	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3843482148			Jun 23 07:53:55 PM PDT 24	Jun 23 07:58:12 PM PDT 24	2712636008 ps
T735	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426074869			Jun 23 08:23:02 PM PDT 24	Jun 23 08:30:02 PM PDT 24	3928785272 ps
T760	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3701207406			Jun 23 08:21:53 PM PDT 24	Jun 23 08:30:33 PM PDT 24	5194278600 ps
T33	/workspace/coverage/default/0.chip_sw_usbdev_dpi.2587186989			Jun 23 07:48:13 PM PDT 24	Jun 23 08:41:07 PM PDT 24	12558007750 ps
T363	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.139510479			Jun 23 07:58:45 PM PDT 24	Jun 23 09:15:15 PM PDT 24	15865193116 ps
T768	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996867590			Jun 23 07:50:43 PM PDT 24	Jun 23 07:58:19 PM PDT 24	3614271818 ps
T123	/workspace/coverage/default/2.chip_sw_edn_boot_mode.3053868985			Jun 23 08:11:23 PM PDT 24	Jun 23 08:22:58 PM PDT 24	2869204336 ps
T229	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.670487943			Jun 23 07:52:04 PM PDT 24	Jun 23 09:22:45 PM PDT 24	47807262488 ps
T385	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2083607268			Jun 23 07:54:56 PM PDT 24	Jun 23 07:59:50 PM PDT 24	2681350600 ps
T213	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2417909681			Jun 23 08:17:31 PM PDT 24	Jun 23 08:55:41 PM PDT 24	13102462780 ps
T26	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2172258980			Jun 23 07:49:19 PM PDT 24	Jun 23 07:55:18 PM PDT 24	2922264738 ps
T937	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1870891512			Jun 23 07:50:47 PM PDT 24	Jun 23 08:01:50 PM PDT 24	4484362856 ps
T938	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.42237612			Jun 23 07:57:03 PM PDT 24	Jun 23 08:44:20 PM PDT 24	12296696270 ps
T199	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1018755492			Jun 23 07:49:52 PM PDT 24	Jun 23 07:56:08 PM PDT 24	3279421631 ps
T211	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.796331166			Jun 23 08:07:22 PM PDT 24	Jun 23 08:20:05 PM PDT 24	4530339190 ps
T939	/workspace/coverage/default/2.chip_sw_example_concurrency.579863572			Jun 23 08:07:02 PM PDT 24	Jun 23 08:13:00 PM PDT 24	3188002432 ps
T220	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2592282618			Jun 23 07:50:48 PM PDT 24	Jun 23 09:10:52 PM PDT 24	16457672452 ps
T338	/workspace/coverage/default/20.chip_sw_all_escalation_resets.713377987			Jun 23 08:19:32 PM PDT 24	Jun 23 08:31:34 PM PDT 24	5654135858 ps
T312	/workspace/coverage/default/2.chip_plic_all_irqs_20.2084085949			Jun 23 08:12:10 PM PDT 24	Jun 23 08:28:24 PM PDT 24	5118765980 ps
T196	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1770326238			Jun 23 08:06:23 PM PDT 24	Jun 23 11:03:59 PM PDT 24	65822319996 ps
T827	/workspace/coverage/default/71.chip_sw_all_escalation_resets.4275921573			Jun 23 08:23:25 PM PDT 24	Jun 23 08:33:30 PM PDT 24	4918427072 ps
T940	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3655780316			Jun 23 08:15:46 PM PDT 24	Jun 23 08:19:58 PM PDT 24	2749641682 ps
T941	/workspace/coverage/default/2.chip_sw_hmac_enc.3331693523			Jun 23 08:11:17 PM PDT 24	Jun 23 08:16:39 PM PDT 24	3189377572 ps
T747	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3112047936			Jun 23 08:13:02 PM PDT 24	Jun 23 08:20:56 PM PDT 24	3460142196 ps
T942	/workspace/coverage/default/0.chip_sw_example_rom.4056326231			Jun 23 07:47:19 PM PDT 24	Jun 23 07:49:29 PM PDT 24	2705591940 ps
T943	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1769887161			Jun 23 07:55:47 PM PDT 24	Jun 23 08:02:59 PM PDT 24	6156695338 ps
T713	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3865144226			Jun 23 08:14:02 PM PDT 24	Jun 23 08:18:01 PM PDT 24	2977002224 ps
T417	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.109285705			Jun 23 07:57:04 PM PDT 24	Jun 23 08:01:01 PM PDT 24	2618438252 ps
T364	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2623276850			Jun 23 07:58:48 PM PDT 24	Jun 23 09:41:50 PM PDT 24	25024033222 ps
T383	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2906343387			Jun 23 07:58:01 PM PDT 24	Jun 23 09:23:56 PM PDT 24	23647548078 ps
T944	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3619141221			Jun 23 08:18:55 PM PDT 24	Jun 23 08:23:11 PM PDT 24	3071243972 ps
T48	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4054561696			Jun 23 07:49:53 PM PDT 24	Jun 23 07:57:19 PM PDT 24	5096503940 ps
T828	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1388145931			Jun 23 08:21:59 PM PDT 24	Jun 23 08:37:02 PM PDT 24	5886437656 ps
T49	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3089351034			Jun 23 08:09:35 PM PDT 24	Jun 23 08:17:46 PM PDT 24	6045398798 ps
T265	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2212060166			Jun 23 08:12:35 PM PDT 24	Jun 23 08:22:33 PM PDT 24	8389266620 ps
T945	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2752848812			Jun 23 08:03:08 PM PDT 24	Jun 23 08:08:57 PM PDT 24	2949379946 ps
T34	/workspace/coverage/default/0.chip_sw_usbdev_config_host.411542874			Jun 23 07:49:00 PM PDT 24	Jun 23 08:21:12 PM PDT 24	7865370134 ps
T946	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1228536088			Jun 23 08:04:44 PM PDT 24	Jun 23 08:10:25 PM PDT 24	3088197680 ps
T27	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4106233640			Jun 23 07:50:22 PM PDT 24	Jun 23 08:01:42 PM PDT 24	4605090633 ps
T947	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.107954321			Jun 23 08:07:27 PM PDT 24	Jun 23 08:12:09 PM PDT 24	2365306310 ps
T792	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3425005324			Jun 23 08:25:30 PM PDT 24	Jun 23 08:34:24 PM PDT 24	5500291152 ps
T178	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.27961527			Jun 23 07:55:40 PM PDT 24	Jun 23 09:24:07 PM PDT 24	43590955911 ps
T948	/workspace/coverage/default/0.chip_sw_hmac_oneshot.2754997214			Jun 23 07:52:25 PM PDT 24	Jun 23 07:59:02 PM PDT 24	2693772002 ps
T949	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3509989510			Jun 23 08:06:22 PM PDT 24	Jun 23 08:19:46 PM PDT 24	4602794384 ps
T368	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3936490327			Jun 23 07:53:57 PM PDT 24	Jun 23 08:02:05 PM PDT 24	5583364380 ps
T950	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.960044349			Jun 23 07:56:32 PM PDT 24	Jun 23 08:01:31 PM PDT 24	3737448376 ps
T214	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.70599103			Jun 23 08:20:02 PM PDT 24	Jun 23 08:46:22 PM PDT 24	8003477080 ps
T738	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1154191131			Jun 23 08:23:56 PM PDT 24	Jun 23 08:31:26 PM PDT 24	4618616700 ps
T951	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.323523549			Jun 23 07:57:44 PM PDT 24	Jun 23 09:02:02 PM PDT 24	15390892600 ps
T952	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2252759076			Jun 23 07:57:51 PM PDT 24	Jun 23 08:56:32 PM PDT 24	16070017100 ps
T156	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2493459650			Jun 23 07:51:44 PM PDT 24	Jun 23 11:01:53 PM PDT 24	256075211188 ps
T200	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.557754545			Jun 23 07:49:45 PM PDT 24	Jun 23 07:59:38 PM PDT 24	4955880409 ps
T260	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1959931423			Jun 23 07:51:36 PM PDT 24	Jun 23 07:54:11 PM PDT 24	2690861866 ps
T807	/workspace/coverage/default/52.chip_sw_all_escalation_resets.805127363			Jun 23 08:22:33 PM PDT 24	Jun 23 08:35:01 PM PDT 24	5555118470 ps
T953	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2398791779			Jun 23 08:09:23 PM PDT 24	Jun 23 08:19:49 PM PDT 24	9705728100 ps
T38	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1859699057			Jun 23 07:48:43 PM PDT 24	Jun 23 09:45:08 PM PDT 24	31453654540 ps
T150	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2722517912			Jun 23 07:59:00 PM PDT 24	Jun 23 08:22:11 PM PDT 24	6785551516 ps
T742	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.491087385			Jun 23 08:22:33 PM PDT 24	Jun 23 08:28:34 PM PDT 24	3629840788 ps
T64	/workspace/coverage/default/4.chip_tap_straps_rma.1025058184			Jun 23 08:17:54 PM PDT 24	Jun 23 08:30:20 PM PDT 24	7067603826 ps
T749	/workspace/coverage/default/50.chip_sw_all_escalation_resets.198507163			Jun 23 08:21:55 PM PDT 24	Jun 23 08:30:45 PM PDT 24	5206180776 ps
T954	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4175865659			Jun 23 07:51:50 PM PDT 24	Jun 23 07:57:48 PM PDT 24	3738569908 ps
T955	/workspace/coverage/default/0.rom_e2e_asm_init_dev.4130181980			Jun 23 07:58:56 PM PDT 24	Jun 23 08:59:19 PM PDT 24	15844006036 ps
T744	/workspace/coverage/default/84.chip_sw_all_escalation_resets.742077602			Jun 23 08:26:45 PM PDT 24	Jun 23 08:37:57 PM PDT 24	5285173512 ps
T956	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2303630566			Jun 23 08:08:39 PM PDT 24	Jun 23 09:20:42 PM PDT 24	15547354586 ps
T748	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056186988			Jun 23 08:21:33 PM PDT 24	Jun 23 08:27:07 PM PDT 24	3958738000 ps
T842	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2637857472			Jun 23 08:24:02 PM PDT 24	Jun 23 08:34:40 PM PDT 24	6020278570 ps
T348	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3321630793			Jun 23 07:55:58 PM PDT 24	Jun 23 08:01:32 PM PDT 24	3582289984 ps
T261	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1530212776			Jun 23 07:59:49 PM PDT 24	Jun 23 08:01:37 PM PDT 24	2976368891 ps
T743	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3347428245			Jun 23 08:24:45 PM PDT 24	Jun 23 08:30:26 PM PDT 24	3249832700 ps
T957	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2935704775			Jun 23 07:52:37 PM PDT 24	Jun 23 09:09:11 PM PDT 24	16273539410 ps
T958	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.380499006			Jun 23 08:12:17 PM PDT 24	Jun 23 08:23:16 PM PDT 24	3766154330 ps
T959	/workspace/coverage/default/0.chip_sw_aes_idle.1004578964			Jun 23 07:49:32 PM PDT 24	Jun 23 07:53:12 PM PDT 24	3164332060 ps
T39	/workspace/coverage/default/1.chip_sw_gpio.865095488			Jun 23 07:54:54 PM PDT 24	Jun 23 08:04:42 PM PDT 24	4580735776 ps
T234	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1662230447			Jun 23 07:48:56 PM PDT 24	Jun 23 07:58:16 PM PDT 24	5552941052 ps
T960	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3664809703			Jun 23 07:58:36 PM PDT 24	Jun 23 08:31:07 PM PDT 24	8538453040 ps
T345	/workspace/coverage/default/24.chip_sw_all_escalation_resets.4065101475			Jun 23 08:20:44 PM PDT 24	Jun 23 08:31:31 PM PDT 24	5638712048 ps