Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	464	1			T72	2		T356	1		T507	1
all_values[1]	450	1			T72	2		T704	1		T509	1
all_values[2]	480	1			T72	3		T507	2		T484	1
all_values[3]	459	1			T72	1		T77	1		T507	2
all_values[4]	500	1			T72	1		T356	1		T507	2
all_values[5]	421	1			T72	2		T704	2		T507	3
all_values[6]	433	1			T72	1		T507	1		T509	1
all_values[7]	449	1			T72	1		T356	1		T509	1
all_values[8]	439	1			T72	2		T704	1		T507	1
all_values[9]	484	1			T72	3		T484	3		T587	2
all_values[10]	447	1			T72	4		T356	1		T507	3
all_values[11]	451	1			T71	1		T72	3		T507	3
all_values[12]	466	1			T750	1		T484	2		T446	2
all_values[13]	449	1			T71	1		T72	5		T507	2
all_values[14]	442	1			T72	3		T507	1		T509	1
all_values[15]	417	1			T72	2		T507	2		T484	1
all_values[16]	440	1			T72	3		T484	2		T587	3
all_values[17]	483	1			T71	2		T72	4		T356	1
all_values[18]	472	1			T72	1		T704	2		T507	3
all_values[19]	455	1			T507	3		T484	1		T587	3
all_values[20]	431	1			T72	1		T356	1		T704	1
all_values[21]	486	1			T72	3		T77	1		T507	1
all_values[22]	465	1			T704	1		T507	1		T484	1
all_values[23]	496	1			T71	1		T72	1		T507	1
all_values[24]	476	1			T72	2		T704	1		T507	3
all_values[25]	445	1			T71	1		T72	1		T507	2
all_values[26]	455	1			T72	4		T507	2		T484	2
all_values[27]	442	1			T72	2		T704	1		T507	1
all_values[28]	443	1			T72	1		T507	2		T587	2
all_values[29]	469	1			T72	1		T704	1		T507	2
all_values[30]	470	1			T72	2		T507	3		T509	1
all_values[31]	480	1			T71	1		T72	4		T507	1
all_values[32]	444	1			T71	1		T72	1		T356	1
all_values[33]	497	1			T71	1		T72	3		T77	1
all_values[34]	493	1			T72	3		T507	2		T484	1
all_values[35]	457	1			T72	5		T507	1		T484	2
all_values[36]	459	1			T71	1		T72	2		T508	1
all_values[37]	443	1			T72	3		T704	2		T507	4
all_values[38]	444	1			T77	1		T356	1		T507	2
all_values[39]	446	1			T72	2		T507	2		T484	1
all_values[40]	459	1			T72	2		T356	1		T507	1
all_values[41]	468	1			T71	1		T72	2		T77	1
all_values[42]	468	1			T72	3		T484	6		T587	1
all_values[43]	454	1			T71	1		T72	1		T507	2
all_values[44]	449	1			T72	1		T509	1		T456	3
all_values[45]	455	1			T72	1		T356	1		T509	1
all_values[46]	466	1			T71	1		T72	2		T509	1
all_values[47]	483	1			T72	1		T507	2		T484	2
all_values[48]	443	1			T72	1		T507	2		T509	1
all_values[49]	448	1			T72	2		T356	1		T507	3