Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3551	1			T72	26		T77	4		T356	3
all_values[1]	3480	1			T72	24		T77	6		T356	3
all_values[2]	3479	1			T72	25		T77	5		T356	3
all_values[3]	3477	1			T72	22		T77	3		T356	4
all_values[4]	3594	1			T72	15		T77	5		T356	5
all_values[5]	3498	1			T72	21		T77	3		T356	5
all_values[6]	3512	1			T72	23		T77	5		T356	3
all_values[7]	3564	1			T72	21		T77	6		T356	2
all_values[8]	3503	1			T72	19		T77	6		T356	2
all_values[9]	3572	1			T72	21		T77	6		T356	2
all_values[10]	3584	1			T72	24		T77	5		T356	3
all_values[11]	3439	1			T72	29		T77	1		T356	5
all_values[12]	3400	1			T72	22		T77	4		T356	1
all_values[13]	3581	1			T72	20		T77	7		T356	5
all_values[14]	3442	1			T72	13		T77	6		T356	2
all_values[15]	3524	1			T72	27		T77	6		T356	3
all_values[16]	3483	1			T72	25		T77	5		T356	1
all_values[17]	3603	1			T72	28		T77	2		T356	2
all_values[18]	3484	1			T72	27		T77	5		T356	3
all_values[19]	3510	1			T72	28		T77	8		T356	2
all_values[20]	3602	1			T72	29		T77	4		T356	4
all_values[21]	3632	1			T72	9		T77	4		T356	5
all_values[22]	3589	1			T72	17		T77	2		T356	2
all_values[23]	3589	1			T72	21		T77	4		T356	1
all_values[24]	3495	1			T72	32		T77	7		T356	1
all_values[25]	3541	1			T72	24		T356	2		T426	2
all_values[26]	3466	1			T72	18		T77	7		T356	2
all_values[27]	3502	1			T72	24		T77	2		T356	3
all_values[28]	3572	1			T72	20		T77	2		T356	5
all_values[29]	3568	1			T72	22		T77	2		T356	3
all_values[30]	3435	1			T72	20		T77	2		T356	2
all_values[31]	3606	1			T72	22		T77	2		T356	2
all_values[32]	3535	1			T72	42		T77	4		T356	2
all_values[33]	3415	1			T72	19		T77	3		T356	2
all_values[34]	3527	1			T72	29		T77	6		T356	2
all_values[35]	3405	1			T72	20		T77	4		T356	2
all_values[36]	3629	1			T72	31		T77	7		T356	7
all_values[37]	3496	1			T72	19		T77	3		T356	1
all_values[38]	3483	1			T72	19		T77	4		T356	2
all_values[39]	3465	1			T72	26		T77	3		T426	1
all_values[40]	3676	1			T72	22		T77	5		T356	3
all_values[41]	3438	1			T72	20		T77	5		T356	4
all_values[42]	3444	1			T72	23		T77	5		T356	6
all_values[43]	3586	1			T72	23		T77	7		T356	2
all_values[44]	3391	1			T72	20		T77	4		T356	2
all_values[45]	3420	1			T72	25		T77	2		T356	1
all_values[46]	3588	1			T72	29		T77	4		T356	1
all_values[47]	3532	1			T72	28		T77	9		T507	12
all_values[48]	3500	1			T72	21		T77	4		T356	2
all_values[49]	3463	1			T72	31		T77	4		T356	3
all_values[50]	3481	1			T72	25		T77	7		T356	1
all_values[51]	3400	1			T72	29		T77	2		T356	1
all_values[52]	3549	1			T72	28		T77	2		T356	1
all_values[53]	3459	1			T72	21		T77	2		T356	3
all_values[54]	3560	1			T72	21		T77	3		T356	1
all_values[55]	3454	1			T72	19		T77	3		T356	3
all_values[56]	3387	1			T72	26		T77	5		T356	2
all_values[57]	3582	1			T72	21		T77	3		T356	3
all_values[58]	3500	1			T72	27		T77	4		T356	2
all_values[59]	3576	1			T72	20		T77	3		T356	3
all_values[60]	3510	1			T72	24		T77	2		T356	5
all_values[61]	3493	1			T72	30		T77	5		T356	4
all_values[62]	3495	1			T72	28		T77	3		T356	3
all_values[63]	3594	1			T72	17		T77	4		T356	2