Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146081	1			T68	1		T70	3		T73	22
values[2]	10151	1			T146	7		T237	1		T425	1
values[3]	3317	1			T516	1		T511	2		T619	73
values[4]	2025	1			T619	37		T405	3		T541	27
values[5]	1317	1			T619	19		T405	3		T541	5
values[6]	958	1			T619	23		T405	2		T541	1
values[7]	641	1			T619	13		T405	1		T554	15
values[8]	505	1			T619	15		T405	1		T554	20
values[9]	469	1			T619	10		T405	3		T554	35
values[10]	387	1			T619	3		T405	5		T554	19
values[11]	369	1			T405	9		T554	25		T411	3
values[12]	326	1			T405	3		T554	15		T411	8
values[13]	281	1			T405	4		T554	10		T411	13
values[14]	303	1			T405	13		T554	13		T411	6
values[15]	302	1			T405	7		T554	15		T411	5
values[16]	256	1			T405	3		T554	6		T411	6
values[17]	288	1			T405	1		T554	15		T411	7
values[18]	283	1			T405	2		T554	20		T411	7
values[19]	259	1			T405	1		T554	16		T411	10
values[20]	257	1			T405	1		T554	27		T411	4
values[21]	257	1			T405	1		T554	24		T411	7
values[22]	245	1			T405	2		T554	11		T411	15
values[23]	210	1			T405	1		T554	4		T411	8
values[24]	222	1			T405	2		T554	5		T411	3
values[25]	243	1			T405	4		T554	6		T411	3
values[26]	211	1			T405	2		T554	7		T411	4
values[27]	267	1			T405	6		T554	13		T411	17
values[28]	231	1			T405	5		T554	10		T411	18
values[29]	221	1			T405	1		T554	7		T411	3
values[30]	222	1			T405	1		T554	7		T411	5
values[31]	213	1			T405	4		T554	5		T411	4
values[32]	211	1			T405	2		T554	5		T411	5
values[33]	232	1			T405	18		T554	4		T411	4
values[34]	221	1			T405	18		T554	5		T411	5
values[35]	304	1			T405	17		T554	5		T411	6
values[36]	242	1			T405	2		T554	8		T411	7
values[37]	179	1			T405	1		T554	6		T411	4
values[38]	200	1			T405	2		T554	2		T411	11
values[39]	198	1			T405	7		T554	10		T411	15
values[40]	193	1			T405	7		T554	9		T411	19
values[41]	250	1			T405	2		T554	14		T411	14
values[42]	222	1			T405	5		T554	5		T411	12
values[43]	203	1			T405	1		T554	4		T411	7
values[44]	292	1			T405	2		T554	9		T411	6
values[45]	212	1			T405	6		T554	6		T411	5
values[46]	201	1			T405	3		T554	13		T411	6
values[47]	216	1			T405	1		T554	6		T411	3
values[48]	227	1			T405	1		T554	7		T411	14
values[49]	185	1			T405	2		T554	4		T411	6
values[50]	204	1			T405	2		T554	3		T411	7
values[51]	232	1			T405	1		T554	7		T411	9
values[52]	196	1			T405	3		T554	4		T411	12
values[53]	194	1			T405	8		T554	12		T411	9
values[54]	215	1			T405	3		T554	5		T411	5
values[55]	214	1			T405	2		T554	7		T411	7
values[56]	173	1			T405	6		T554	7		T411	4
values[57]	210	1			T405	7		T554	8		T411	7
values[58]	192	1			T405	3		T554	3		T411	8
values[59]	148	1			T405	2		T554	11		T411	7
values[60]	165	1			T405	4		T554	8		T411	10
values[61]	138	1			T405	2		T554	9		T411	6
values[62]	163	1			T405	2		T554	11		T411	30
values[63]	120	1			T405	2		T554	7		T411	3
values[64]	144	1			T405	1		T554	3		T411	6
values[65]	101	1			T405	1		T411	8		T762	1
values[66]	88	1			T405	4		T411	1		T762	1
values[67]	117	1			T405	2		T762	1		T533	2
values[68]	109	1			T405	3		T762	1		T533	2
values[69]	114	1			T405	2		T762	1		T533	2
values[70]	112	1			T405	4		T762	1		T533	2
values[71]	93	1			T405	11		T762	1		T533	2
values[72]	70	1			T405	9		T762	1		T533	2
values[73]	76	1			T405	6		T762	1		T533	2
values[74]	85	1			T405	3		T762	1		T533	3
values[75]	99	1			T405	4		T762	1		T533	2
values[76]	68	1			T405	1		T762	1		T533	2
values[77]	53	1			T405	5		T762	1		T533	2
values[78]	73	1			T405	7		T762	1		T533	2
values[79]	70	1			T405	4		T762	1		T533	2
values[80]	70	1			T405	8		T762	1		T533	2
values[81]	76	1			T405	7		T762	1		T533	2
values[82]	50	1			T405	1		T762	1		T533	2
values[83]	71	1			T405	4		T762	1		T533	2
values[84]	66	1			T405	8		T762	1		T533	2
values[85]	72	1			T405	5		T762	1		T533	2
values[86]	66	1			T405	10		T762	1		T533	2
values[87]	68	1			T405	1		T762	1		T533	2
values[88]	71	1			T405	2		T762	1		T533	2
values[89]	77	1			T405	3		T762	1		T533	2
values[90]	82	1			T405	7		T762	1		T533	2
values[91]	76	1			T405	6		T762	1		T533	2
values[92]	66	1			T405	7		T762	1		T533	2
values[93]	57	1			T405	1		T762	1		T533	2
values[94]	61	1			T405	3		T762	2		T533	2
values[95]	79	1			T405	10		T762	3		T533	2
values[96]	59	1			T405	3		T762	4		T533	2
values[97]	54	1			T405	4		T762	1		T533	2
values[98]	68	1			T405	2		T762	8		T533	2
values[99]	75	1			T405	3		T762	5		T533	2
values[100]	81	1			T405	14		T762	4		T533	3
values[101]	79	1			T405	9		T762	2		T533	2
values[102]	63	1			T405	5		T762	3		T533	2
values[103]	54	1			T405	6		T762	1		T533	2
values[104]	47	1			T405	6		T762	2		T533	2
values[105]	46	1			T405	5		T762	1		T533	2
values[106]	49	1			T405	3		T762	1		T533	4
values[107]	66	1			T405	4		T762	2		T533	2
values[108]	54	1			T405	2		T762	1		T533	3
values[109]	37	1			T405	4		T762	2		T533	2
values[110]	44	1			T405	2		T762	3		T533	3
values[111]	47	1			T405	3		T762	3		T533	4
values[112]	51	1			T405	2		T762	3		T533	3
values[113]	39	1			T405	3		T762	3		T533	2
values[114]	41	1			T405	4		T762	1		T533	8
values[115]	35	1			T405	3		T762	1		T533	4
values[116]	52	1			T405	5		T762	2		T533	5
values[117]	55	1			T405	5		T762	6		T533	2
values[118]	42	1			T405	5		T762	1		T533	4
values[119]	43	1			T405	5		T762	1		T533	3
values[120]	41	1			T405	2		T762	1		T533	3
values[121]	42	1			T405	3		T762	1		T533	4
values[122]	60	1			T405	4		T762	5		T533	11
values[123]	54	1			T762	1		T533	2		T780	2
values[124]	51	1			T762	1		T533	7		T780	4
values[125]	60	1			T762	1		T533	6		T780	4
values[126]	97	1			T762	2		T533	7		T780	3
values[127]	582	1			T762	24		T533	71		T780	40
values[128]	4196	1			T762	255		T533	553		T780	394