Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.39	93.96	95.30		94.85	97.53	99.55

Total tests in report: 2866

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.54	39.54	44.96	44.96	43.06	43.06	31.45	31.45			57.96	57.96	59.44	59.44	0.39	0.39	/workspace/coverage/default/47.chip_sw_all_escalation_resets.924515629
52.73	13.18	58.84	13.88	59.39	16.33	39.06	7.61			72.47	14.51	85.84	26.40	0.76	0.38	/workspace/coverage/default/2.chip_jtag_csr_rw.1732069216
58.26	5.53	58.91	0.07	60.91	1.52	39.51	0.45			72.49	0.02	85.84	0.00	31.89	31.12	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.72377272
63.59	5.33	70.45	11.54	68.32	7.41	42.35	2.84			82.69	10.20	85.84	0.00	31.89	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2853923568
67.20	3.61	76.67	6.22	70.22	1.90	47.01	4.67			82.86	0.17	85.84	0.00	40.59	8.71	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2869561148
70.59	3.39	82.57	5.90	74.47	4.25	51.00	3.98			84.85	1.99	90.03	4.20	40.59	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3727937945
73.81	3.22	82.57	0.00	74.53	0.06	51.00	0.00			84.87	0.02	90.03	0.00	59.86	19.27	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1833975651
76.39	2.58	82.57	0.00	74.53	0.00	66.47	15.48			84.87	0.00	90.03	0.00	59.86	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.834349773
78.65	2.26	82.57	0.00	74.80	0.27	66.47	0.00			84.96	0.10	90.03	0.00	73.05	13.18	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3258776988
80.35	1.71	84.56	1.99	76.15	1.35	71.74	5.27			86.06	1.10	90.56	0.52	73.05	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.949126082
81.94	1.59	84.56	0.00	76.15	0.00	71.74	0.00			86.06	0.00	90.56	0.00	82.60	9.55	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.506570298
83.26	1.31	84.64	0.08	76.15	0.01	79.53	7.79			86.07	0.01	90.56	0.00	82.60	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.354993797
84.49	1.23	86.98	2.34	78.04	1.89	80.42	0.89			88.36	2.29	90.56	0.00	82.60	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2779231937
85.58	1.09	87.68	0.69	82.78	4.74	80.61	0.19			88.45	0.10	90.56	0.00	83.40	0.80	/workspace/coverage/cover_reg_top/8.chip_tl_errors.4227751390
86.60	1.02	87.68	0.01	82.85	0.07	81.11	0.50			88.46	0.01	90.56	0.00	88.94	5.55	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1559463339
87.61	1.01	88.78	1.10	84.86	2.01	81.27	0.16			90.55	2.09	91.26	0.70	88.94	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2487673127
88.46	0.85	88.79	0.02	84.91	0.05	83.83	2.57			90.55	0.00	91.26	0.00	91.43	2.49	/workspace/coverage/default/2.chip_sw_alert_test.1535212481
89.21	0.75	89.12	0.33	85.05	0.15	83.85	0.01			90.72	0.17	95.10	3.85	91.43	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1977338702
89.90	0.68	90.29	1.16	86.25	1.19	84.57	0.72			91.75	1.03	95.10	0.00	91.43	0.00	/workspace/coverage/default/2.chip_sw_gpio.3708275404
90.42	0.52	91.11	0.82	88.09	1.84	84.64	0.07			92.16	0.41	95.10	0.00	91.43	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4283194384
90.91	0.48	91.11	0.00	88.17	0.08	84.64	0.00			92.18	0.02	95.10	0.00	94.24	2.81	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2321256872
91.37	0.46	91.11	0.00	88.17	0.00	84.64	0.00			92.18	0.00	95.10	0.00	97.00	2.76	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.412882923
91.79	0.42	91.68	0.57	88.67	0.49	85.01	0.37			92.75	0.57	95.63	0.52	97.00	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.47306121
92.19	0.40	92.23	0.56	89.22	0.55	85.70	0.69			93.33	0.58	95.63	0.00	97.00	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2232429485
92.58	0.39	92.24	0.01	89.22	0.01	88.05	2.35			93.33	0.00	95.63	0.00	97.00	0.00	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2112928836
92.90	0.32	93.15	0.90	89.47	0.25	88.37	0.33			93.40	0.07	95.98	0.35	97.00	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4092810314
93.17	0.27	93.79	0.64	89.80	0.33	88.65	0.27			93.61	0.20	96.15	0.17	97.02	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.329832326
93.42	0.25	93.79	0.00	89.80	0.00	90.16	1.52			93.61	0.00	96.15	0.00	97.02	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.599760956
93.59	0.17	93.79	0.00	89.84	0.04	90.18	0.02			93.62	0.02	96.15	0.00	97.94	0.93	/workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2752636499
93.74	0.15	94.00	0.21	90.16	0.32	90.54	0.36			93.62	0.00	96.15	0.00	97.94	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2521613480
93.87	0.14	94.01	0.01	90.53	0.37	90.56	0.02			94.04	0.42	96.15	0.00	97.94	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3544179815
93.98	0.11	94.01	0.00	90.53	0.00	91.21	0.65			94.04	0.00	96.15	0.00	97.94	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1636823682
94.09	0.11	94.01	0.00	90.53	0.00	91.86	0.65			94.04	0.00	96.15	0.00	97.94	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1174220973
94.19	0.10	94.01	0.00	91.16	0.63	91.86	0.00			94.04	0.00	96.15	0.00	97.94	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1294852073
94.30	0.10	94.03	0.02	91.16	0.01	92.45	0.59			94.04	0.00	96.15	0.00	97.94	0.00	/workspace/coverage/default/30.chip_sw_all_escalation_resets.4245101997
94.40	0.10	94.12	0.09	91.20	0.04	92.57	0.12			94.07	0.02	96.50	0.35	97.94	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3475700241
94.50	0.10	94.20	0.08	91.56	0.36	92.59	0.02			94.22	0.15	96.50	0.00	97.94	0.00	/workspace/coverage/cover_reg_top/19.chip_csr_rw.3120843247
94.59	0.08	94.20	0.01	91.57	0.02	92.90	0.31			94.22	0.00	96.68	0.17	97.94	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3436159737
94.64	0.06	94.29	0.09	91.64	0.06	93.05	0.15			94.25	0.03	96.68	0.00	97.94	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2188117996
94.70	0.05	94.29	0.00	91.78	0.14	93.06	0.01			94.42	0.16	96.68	0.00	97.94	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.349347985
94.75	0.05	94.29	0.00	91.86	0.08	93.06	0.00			94.42	0.00	96.68	0.00	98.17	0.22	/workspace/coverage/cover_reg_top/35.xbar_stress_all.2415382643
94.79	0.05	94.32	0.03	91.88	0.02	93.12	0.05			94.43	0.02	96.85	0.17	98.17	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2086111706
94.84	0.05	94.37	0.05	92.02	0.14	93.12	0.00			94.51	0.08	96.85	0.00	98.17	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1925650372
94.88	0.04	94.37	0.00	92.28	0.26	93.12	0.00			94.51	0.00	96.85	0.00	98.17	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.645601757
94.92	0.04	94.38	0.01	92.37	0.10	93.26	0.14			94.52	0.01	96.85	0.00	98.17	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3208638433
94.97	0.04	94.38	0.00	92.37	0.00	93.50	0.25			94.52	0.00	96.85	0.00	98.17	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1672980024
95.00	0.04	94.39	0.01	92.39	0.01	93.50	0.00			94.55	0.02	97.03	0.17	98.18	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193621035
95.04	0.04	94.39	0.01	92.40	0.01	93.51	0.01			94.55	0.01	97.20	0.17	98.19	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1026977839
95.08	0.04	94.40	0.01	92.41	0.01	93.51	0.00			94.56	0.01	97.38	0.17	98.20	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082991681
95.11	0.04	94.40	0.00	92.41	0.00	93.55	0.04			94.56	0.00	97.55	0.17	98.20	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2299271883
95.14	0.03	94.40	0.00	92.60	0.19	93.55	0.00			94.56	0.00	97.55	0.00	98.20	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2680569278
95.17	0.03	94.40	0.00	92.60	0.00	93.73	0.18			94.56	0.00	97.55	0.00	98.20	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1076392088
95.20	0.03	94.40	0.00	92.60	0.00	93.91	0.18			94.56	0.00	97.55	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3829915755
95.23	0.03	94.47	0.07	92.63	0.03	93.93	0.03			94.61	0.05	97.55	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3304771925
95.26	0.03	94.47	0.00	92.63	0.00	94.11	0.18			94.61	0.00	97.55	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.635248769
95.29	0.03	94.47	0.00	92.63	0.00	94.28	0.17			94.61	0.00	97.55	0.00	98.20	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.2498666282
95.32	0.03	94.48	0.01	92.63	0.00	94.41	0.13			94.61	0.00	97.55	0.00	98.23	0.02	/workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1462244634
95.35	0.03	94.48	0.00	92.69	0.06	94.41	0.00			94.63	0.02	97.55	0.00	98.32	0.09	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2857997992
95.37	0.03	94.55	0.07	92.69	0.00	94.49	0.08			94.64	0.01	97.55	0.00	98.32	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.554889959
95.40	0.03	94.57	0.02	92.78	0.09	94.51	0.01			94.66	0.02	97.55	0.00	98.32	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1136016639
95.42	0.02	94.64	0.07	92.83	0.05	94.51	0.00			94.69	0.03	97.55	0.00	98.32	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3875718222
95.45	0.02	94.64	0.00	92.84	0.01	94.51	0.00			94.69	0.00	97.55	0.00	98.45	0.13	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1271964794
95.47	0.02	94.64	0.00	92.94	0.10	94.51	0.00			94.73	0.03	97.55	0.00	98.45	0.00	/workspace/coverage/cover_reg_top/82.xbar_stress_all.981502849
95.49	0.02	94.64	0.00	93.05	0.11	94.51	0.00			94.73	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3120381617
95.51	0.02	94.64	0.00	93.05	0.00	94.62	0.11			94.73	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3089232657
95.53	0.02	94.64	0.00	93.08	0.02	94.71	0.09			94.73	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3751834411
95.54	0.02	94.64	0.00	93.17	0.10	94.71	0.00			94.73	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3134623970
95.56	0.02	94.64	0.00	93.21	0.03	94.71	0.00			94.74	0.02	97.55	0.00	98.50	0.05	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3199250300
95.57	0.01	94.66	0.02	93.23	0.02	94.71	0.01			94.77	0.02	97.55	0.00	98.51	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3568129117
95.58	0.01	94.68	0.02	93.26	0.03	94.74	0.03			94.77	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1247474297
95.60	0.01	94.68	0.00	93.34	0.08	94.74	0.00			94.77	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2622193357
95.61	0.01	94.69	0.01	93.38	0.04	94.74	0.00			94.79	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2680212784
95.62	0.01	94.69	0.00	93.38	0.00	94.74	0.00			94.79	0.00	97.55	0.00	98.58	0.07	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.410932536
95.63	0.01	94.71	0.01	93.41	0.03	94.75	0.01			94.81	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2932824166
95.64	0.01	94.71	0.00	93.45	0.05	94.75	0.00			94.82	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/69.xbar_stress_all.824362484
95.65	0.01	94.71	0.00	93.46	0.01	94.75	0.00			94.82	0.00	97.55	0.00	98.63	0.05	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.432536660
95.66	0.01	94.73	0.02	93.46	0.01	94.75	0.01			94.84	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3767651873
95.67	0.01	94.74	0.01	93.46	0.00	94.78	0.03			94.84	0.00	97.55	0.00	98.64	0.01	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3939780314
95.68	0.01	94.74	0.00	93.50	0.04	94.78	0.00			94.84	0.00	97.55	0.00	98.65	0.01	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2961826660
95.68	0.01	94.74	0.00	93.50	0.00	94.82	0.05			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.402525316
95.69	0.01	94.74	0.00	93.50	0.00	94.87	0.05			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.484238917
95.70	0.01	94.74	0.00	93.50	0.00	94.91	0.04			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3356951838
95.71	0.01	94.74	0.00	93.54	0.04	94.91	0.00			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1938990754
95.71	0.01	94.74	0.00	93.58	0.04	94.91	0.00			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1774201261
95.72	0.01	94.75	0.01	93.58	0.00	94.94	0.03			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_power_sleep_load.3994268717
95.72	0.01	94.75	0.00	93.61	0.04	94.94	0.00			94.84	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all.1175998501
95.73	0.01	94.75	0.00	93.64	0.02	94.94	0.00			94.84	0.00	97.55	0.00	98.66	0.01	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1146859356
95.73	0.01	94.75	0.00	93.67	0.03	94.94	0.00			94.84	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1541222436
95.74	0.01	94.76	0.01	93.68	0.01	94.95	0.01			94.84	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.472013083
95.74	0.01	94.76	0.00	93.71	0.03	94.95	0.00			94.84	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1755074829
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95.96	0.01	94.77	0.00	93.83	0.00	95.23	0.00			94.84	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1717000770
95.96	0.01	94.77	0.00	93.83	0.00	95.23	0.00			94.84	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.955250759
95.96	0.01	94.77	0.00	93.83	0.00	95.23	0.00			94.84	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909314755
95.96	0.01	94.77	0.00	93.83	0.00	95.23	0.00			94.84	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2976914020
95.96	0.01	94.77	0.00	93.83	0.00	95.24	0.01			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.2812852553
95.97	0.01	94.77	0.00	93.84	0.01	95.24	0.00			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4057131844
95.97	0.01	94.77	0.00	93.85	0.01	95.24	0.00			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.4001965209
95.97	0.01	94.77	0.00	93.86	0.01	95.24	0.00			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.627821882
95.97	0.01	94.77	0.00	93.87	0.01	95.24	0.00			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3002769423
95.97	0.01	94.78	0.01	93.88	0.01	95.24	0.00			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.1993085635
95.98	0.01	94.79	0.01	93.88	0.00	95.24	0.00			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1260668892
95.98	0.01	94.79	0.00	93.88	0.00	95.25	0.01			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.504969040
95.98	0.01	94.79	0.00	93.88	0.01	95.26	0.01			94.84	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1222793874
95.98	0.01	94.79	0.00	93.88	0.00	95.26	0.00			94.85	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2264977874
95.98	0.01	94.79	0.00	93.89	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all.1827811786
95.98	0.01	94.79	0.00	93.89	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/11.xbar_smoke.2560048298
95.98	0.01	94.79	0.00	93.90	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/67.xbar_stress_all.1983123246
95.98	0.01	94.79	0.00	93.91	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2818883755
95.99	0.01	94.79	0.00	93.92	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1484068214
95.99	0.01	94.79	0.00	93.92	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1945273796
95.99	0.01	94.79	0.00	93.92	0.00	95.26	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1456991206
95.99	0.01	94.79	0.01	93.93	0.01	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2019799011
95.99	0.01	94.80	0.01	93.93	0.00	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2471896650
95.99	0.01	94.81	0.01	93.93	0.00	95.26	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.922347048
95.99	0.01	94.81	0.00	93.93	0.00	95.27	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3143723191
95.99	0.01	94.81	0.00	93.93	0.00	95.27	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2398614690
95.99	0.01	94.81	0.00	93.93	0.00	95.28	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4099407614
95.99	0.01	94.81	0.00	93.93	0.00	95.28	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1352236301
96.00	0.01	94.81	0.00	93.93	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.4235356586
96.00	0.01	94.81	0.00	93.93	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3671154468
96.00	0.01	94.81	0.00	93.94	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3408610951
96.00	0.01	94.81	0.00	93.94	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2851256128
96.00	0.01	94.81	0.00	93.94	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3303309483
96.00	0.01	94.81	0.00	93.95	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.827956616
96.00	0.01	94.81	0.00	93.95	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_gpio.1408388109
96.00	0.01	94.81	0.00	93.95	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.628488798
96.00	0.01	94.81	0.00	93.96	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.183232716
96.00	0.01	94.81	0.00	93.96	0.01	95.28	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.295235642
96.00	0.01	94.81	0.00	93.96	0.00	95.29	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.1315406356
96.00	0.01	94.81	0.01	93.96	0.00	95.29	0.00			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.463726822
96.00	0.01	94.81	0.00	93.96	0.00	95.29	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.742034740
96.00	0.01	94.81	0.00	93.96	0.00	95.29	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2749484165
96.00	0.01	94.81	0.00	93.96	0.00	95.29	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.156296575
96.00	0.01	94.81	0.00	93.96	0.00	95.30	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.306969630
96.00	0.01	94.81	0.00	93.96	0.00	95.30	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3142505901
96.00	0.01	94.81	0.00	93.96	0.00	95.30	0.01			94.85	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1975303582

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.637342563
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1515130200
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1668155210
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1797619840
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2026734907
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2700829356
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.679582806
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2289465003
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4274863083
/workspace/coverage/cover_reg_top/0.xbar_error_random.3724247888
/workspace/coverage/cover_reg_top/0.xbar_random.1717310244
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.676320895
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.922448041
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2124306689
/workspace/coverage/cover_reg_top/0.xbar_same_source.1112698081
/workspace/coverage/cover_reg_top/0.xbar_smoke.3825447712
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3756861704
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3000438274
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1158733623
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.207734877
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3234895724
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3453942914
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2843045403
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4069616211
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3234107897
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2727225582
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1257046413
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1293377830
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2812328326
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3014096373
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3252125341
/workspace/coverage/cover_reg_top/1.xbar_error_random.2763653451
/workspace/coverage/cover_reg_top/1.xbar_random.3593300903
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.955835234
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1750002424
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2558813987
/workspace/coverage/cover_reg_top/1.xbar_same_source.109432035
/workspace/coverage/cover_reg_top/1.xbar_smoke.465314926
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2822238663
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1646836395
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2020881786
/workspace/coverage/cover_reg_top/1.xbar_stress_all.4134282562
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1474157601
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2497421243
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.641098618
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3058001624
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1416850112
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2664819061
/workspace/coverage/cover_reg_top/10.chip_tl_errors.4182387190
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.101019142
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.550480724
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.471010118
/workspace/coverage/cover_reg_top/10.xbar_error_random.2769386458
/workspace/coverage/cover_reg_top/10.xbar_random.3062156868
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2213078939
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2164015753
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2026703058
/workspace/coverage/cover_reg_top/10.xbar_same_source.2553125856
/workspace/coverage/cover_reg_top/10.xbar_smoke.2114504987
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.263729431
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2526623381
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3511081469
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3468446371
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3315711739
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3134363581
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2657678432
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2389695124
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1953733256
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.380330567
/workspace/coverage/cover_reg_top/11.chip_tl_errors.750018686
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1450131628
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2577665540
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2059786490
/workspace/coverage/cover_reg_top/11.xbar_error_random.378611305
/workspace/coverage/cover_reg_top/11.xbar_random.936585322
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1482549697
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2792341764
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.500965825
/workspace/coverage/cover_reg_top/11.xbar_same_source.2627632225
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1554395223
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.286225173
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.311601318
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3126461047
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.99413693
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1074049571
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2818199570
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2760158261
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2311683578
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1481112094
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1291452875
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1161281945
/workspace/coverage/cover_reg_top/12.xbar_error_random.283206414
/workspace/coverage/cover_reg_top/12.xbar_random.2298982105
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3621460492
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3957860942
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1113960924
/workspace/coverage/cover_reg_top/12.xbar_same_source.1513450195
/workspace/coverage/cover_reg_top/12.xbar_smoke.808377867
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2388241838
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1551796877
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4099763743
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4032742406
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3306053254
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3609427835
/workspace/coverage/cover_reg_top/13.chip_csr_rw.106931771
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.4238287342
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1901915740
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1982435257
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4102847808
/workspace/coverage/cover_reg_top/13.xbar_error_random.3470262835
/workspace/coverage/cover_reg_top/13.xbar_random.3658803241
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1492323246
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2424261652
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3275407794
/workspace/coverage/cover_reg_top/13.xbar_same_source.1556584218
/workspace/coverage/cover_reg_top/13.xbar_smoke.264950995
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3235364278
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2958865016
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3461874851
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1785713801
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.506470814
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1087652846
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1730583144
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1686798345
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1515892639
/workspace/coverage/cover_reg_top/14.chip_tl_errors.968662793
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2182930932
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.748998648
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3089069494
/workspace/coverage/cover_reg_top/14.xbar_error_random.2167359076
/workspace/coverage/cover_reg_top/14.xbar_random.300864626
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.566578827
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/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128200999
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/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2957228007
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2160810930
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/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2831382465
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1753661368
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.807030044
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.3207401856
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3907988252
/workspace/coverage/default/32.chip_sw_all_escalation_resets.744189668
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1307340944
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.555639715
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3819593714
/workspace/coverage/default/36.chip_sw_all_escalation_resets.4290314831
/workspace/coverage/default/37.chip_sw_all_escalation_resets.4118434322
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2425333734
/workspace/coverage/default/38.chip_sw_all_escalation_resets.4199967955
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2512653513
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1327569180
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1346186805
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4255726212
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1999054673
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2095694825
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3697317809
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3638084434
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4211246237
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1183759578
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2921426470
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3277824915
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3015491494
/workspace/coverage/default/4.chip_tap_straps_dev.860909564
/workspace/coverage/default/4.chip_tap_straps_prod.342449225
/workspace/coverage/default/40.chip_sw_all_escalation_resets.123457228
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2743194489
/workspace/coverage/default/42.chip_sw_all_escalation_resets.23079408
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288440206
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3298223415
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117554042
/workspace/coverage/default/45.chip_sw_all_escalation_resets.154400101
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1177276630
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2379655802
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4118463115
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1037978523
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713974948
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2081687155
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1632322936
/workspace/coverage/default/5.chip_sw_all_escalation_resets.365347635
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1193589841
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4280749446
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1300138852
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3376893315
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.481608751
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2990380955
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1672846583
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3601140621
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3601973797
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2264863216
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1497246039
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2241330479
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290849814
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1515576836
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3442888258
/workspace/coverage/default/6.chip_sw_all_escalation_resets.632796526
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1617410574
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3332651001
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2936914701
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4123655293
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3066161999
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4147359900
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4060087973
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1651602739
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348353425
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.86856312
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1425016270
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1361670776
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3682203260
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.375236880
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2350447555
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.367929123
/workspace/coverage/default/68.chip_sw_all_escalation_resets.32448354
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.348814899
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536098220
/workspace/coverage/default/7.chip_sw_all_escalation_resets.565035852
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2622723166
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.288185434
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2111846043
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2670519417
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2966946843
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1830837657
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090313982
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2059568244
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4130907823
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2682219687
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1687775703
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1966806371
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2709972782
/workspace/coverage/default/76.chip_sw_all_escalation_resets.180485059
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2981715122
/workspace/coverage/default/77.chip_sw_all_escalation_resets.722456520
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3327737741
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1013905658
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.793954177
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1142309139
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409482527
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.61823981
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.445291006
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1094092269
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2430076138
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2990373219
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304903400
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1153379851
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614041777
/workspace/coverage/default/82.chip_sw_all_escalation_resets.569309515
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2108777015
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1377652532
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1790527751
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1089815432
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1161687426
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3507576276
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444475039
/workspace/coverage/default/86.chip_sw_all_escalation_resets.409186650
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1526159987
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515373050
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4170617438
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2726822694
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1540363955
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157858295
/workspace/coverage/default/9.chip_sw_all_escalation_resets.220487992
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3636956997
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2520443912
/workspace/coverage/default/90.chip_sw_all_escalation_resets.539616287
/workspace/coverage/default/91.chip_sw_all_escalation_resets.272252776
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2433058659
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2297515783
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3685297829
/workspace/coverage/default/95.chip_sw_all_escalation_resets.974880690
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1344085714
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3685953848
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3369251025
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3245063897
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.911076290
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.80908690
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2532008197
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1900973057
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2746471253
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3014474921
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1819501313

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Total test records in report: 2866

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2970869493			Jun 24 08:11:41 PM PDT 24	Jun 24 08:16:39 PM PDT 24	2502862664 ps
T5	/workspace/coverage/default/0.chip_jtag_csr_rw.2812852553			Jun 24 07:57:31 PM PDT 24	Jun 24 08:01:58 PM PDT 24	4875469144 ps
T6	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.348814899			Jun 24 08:41:15 PM PDT 24	Jun 24 08:47:52 PM PDT 24	3743280584 ps
T18	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3332651001			Jun 24 08:37:01 PM PDT 24	Jun 24 08:53:21 PM PDT 24	10453867682 ps
T19	/workspace/coverage/default/47.chip_sw_all_escalation_resets.924515629			Jun 24 08:38:12 PM PDT 24	Jun 24 08:47:46 PM PDT 24	5926716536 ps
T80	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2816581753			Jun 24 08:22:16 PM PDT 24	Jun 24 08:33:06 PM PDT 24	3686779329 ps
T20	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.599760956			Jun 24 08:22:37 PM PDT 24	Jun 24 09:37:54 PM PDT 24	42647827562 ps
T81	/workspace/coverage/default/0.chip_sw_kmac_entropy.2498666282			Jun 24 08:04:28 PM PDT 24	Jun 24 08:08:53 PM PDT 24	2967279160 ps
T82	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4181599368			Jun 24 08:06:07 PM PDT 24	Jun 24 08:41:29 PM PDT 24	10659344956 ps
T83	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2086111706			Jun 24 08:25:54 PM PDT 24	Jun 24 08:35:50 PM PDT 24	5656405330 ps
T75	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.329832326			Jun 24 08:38:11 PM PDT 24	Jun 24 08:44:49 PM PDT 24	4301679752 ps
T53	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.949126082			Jun 24 08:26:02 PM PDT 24	Jun 24 09:23:00 PM PDT 24	15839649514 ps
T61	/workspace/coverage/default/30.chip_sw_all_escalation_resets.4245101997			Jun 24 08:36:57 PM PDT 24	Jun 24 08:48:56 PM PDT 24	4238711380 ps
T85	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2112928836			Jun 24 08:37:23 PM PDT 24	Jun 24 09:45:37 PM PDT 24	17775547660 ps
T86	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3969045206			Jun 24 08:33:40 PM PDT 24	Jun 24 08:39:35 PM PDT 24	3982936016 ps
T62	/workspace/coverage/default/45.chip_sw_all_escalation_resets.154400101			Jun 24 08:39:09 PM PDT 24	Jun 24 08:47:40 PM PDT 24	4768068640 ps
T87	/workspace/coverage/default/1.chip_sw_uart_tx_rx.3448621547			Jun 24 08:10:04 PM PDT 24	Jun 24 08:20:33 PM PDT 24	3841587084 ps
T88	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.213051042			Jun 24 08:12:13 PM PDT 24	Jun 24 08:34:02 PM PDT 24	8623427932 ps
T89	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3051267039			Jun 24 08:18:58 PM PDT 24	Jun 24 08:27:57 PM PDT 24	4215190784 ps
T90	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.784112771			Jun 24 08:27:02 PM PDT 24	Jun 24 08:37:56 PM PDT 24	5711228800 ps
T123	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3304771925			Jun 24 08:26:13 PM PDT 24	Jun 24 08:47:10 PM PDT 24	8491655252 ps
T117	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1527806699			Jun 24 08:21:47 PM PDT 24	Jun 24 08:28:12 PM PDT 24	5083094872 ps
T421	/workspace/coverage/default/2.chip_sw_kmac_smoketest.2472483839			Jun 24 08:30:33 PM PDT 24	Jun 24 08:35:34 PM PDT 24	3031417240 ps
T60	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.354993797			Jun 24 08:23:30 PM PDT 24	Jun 24 09:59:30 PM PDT 24	48743083360 ps
T112	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.332497504			Jun 24 08:22:39 PM PDT 24	Jun 24 08:38:24 PM PDT 24	7659301225 ps
T107	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2994309376			Jun 24 08:29:25 PM PDT 24	Jun 24 08:50:50 PM PDT 24	7392112267 ps
T207	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1540363955			Jun 24 08:43:10 PM PDT 24	Jun 24 08:52:56 PM PDT 24	5400487720 ps
T183	/workspace/coverage/default/3.chip_tap_straps_prod.3674022240			Jun 24 08:30:55 PM PDT 24	Jun 24 08:33:38 PM PDT 24	3087375739 ps
T144	/workspace/coverage/default/2.chip_sw_power_idle_load.335371888			Jun 24 08:29:41 PM PDT 24	Jun 24 08:41:03 PM PDT 24	4528556046 ps
T1	/workspace/coverage/default/2.chip_jtag_csr_rw.1732069216			Jun 24 08:20:31 PM PDT 24	Jun 24 08:56:47 PM PDT 24	19469116109 ps
T351	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290849814			Jun 24 08:39:22 PM PDT 24	Jun 24 08:45:33 PM PDT 24	4335350018 ps
T352	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2897446241			Jun 24 08:37:16 PM PDT 24	Jun 24 08:48:07 PM PDT 24	5067239880 ps
T113	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1047580062			Jun 24 08:16:30 PM PDT 24	Jun 24 08:29:25 PM PDT 24	4820911500 ps
T325	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1340839354			Jun 24 08:23:03 PM PDT 24	Jun 24 08:28:08 PM PDT 24	2972567000 ps
T353	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1676142746			Jun 24 08:02:51 PM PDT 24	Jun 24 09:37:17 PM PDT 24	29171026984 ps
T354	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288440206			Jun 24 08:38:57 PM PDT 24	Jun 24 08:46:04 PM PDT 24	3264885420 ps
T118	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3393302975			Jun 24 08:12:36 PM PDT 24	Jun 24 09:04:02 PM PDT 24	34995562989 ps
T208	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2271308657			Jun 24 08:20:54 PM PDT 24	Jun 24 08:38:09 PM PDT 24	6042258160 ps
T355	/workspace/coverage/default/1.chip_sw_aes_enc.4126979606			Jun 24 08:12:37 PM PDT 24	Jun 24 08:17:04 PM PDT 24	3180408668 ps
T293	/workspace/coverage/default/0.chip_plic_all_irqs_20.2853923568			Jun 24 08:05:38 PM PDT 24	Jun 24 08:19:50 PM PDT 24	4403315770 ps
T54	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.972681286			Jun 24 08:35:08 PM PDT 24	Jun 24 09:40:56 PM PDT 24	15535892252 ps
T154	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2188117996			Jun 24 08:22:35 PM PDT 24	Jun 24 08:44:03 PM PDT 24	8735736350 ps
T343	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3568129117			Jun 24 08:39:07 PM PDT 24	Jun 24 08:48:58 PM PDT 24	4124466654 ps
T378	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909314755			Jun 24 08:41:28 PM PDT 24	Jun 24 08:47:35 PM PDT 24	3566993024 ps
T161	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1174220973			Jun 24 08:04:38 PM PDT 24	Jun 24 09:30:43 PM PDT 24	51035762714 ps
T67	/workspace/coverage/default/0.chip_tap_straps_dev.1670616125			Jun 24 08:07:30 PM PDT 24	Jun 24 08:19:58 PM PDT 24	7750188942 ps
T240	/workspace/coverage/default/0.chip_sw_rv_timer_irq.2571154287			Jun 24 08:04:06 PM PDT 24	Jun 24 08:09:12 PM PDT 24	2377655676 ps
T108	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.872267625			Jun 24 08:05:59 PM PDT 24	Jun 24 08:18:05 PM PDT 24	3571054816 ps
T155	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4184260936			Jun 24 08:12:18 PM PDT 24	Jun 24 08:44:24 PM PDT 24	12792802988 ps
T109	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3829915755			Jun 24 08:17:52 PM PDT 24	Jun 24 08:22:03 PM PDT 24	2991858454 ps
T176	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1563091691			Jun 24 08:26:31 PM PDT 24	Jun 24 08:33:23 PM PDT 24	3932154746 ps
T114	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3751834411			Jun 24 08:09:05 PM PDT 24	Jun 24 08:23:52 PM PDT 24	7916023205 ps
T245	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3581502094			Jun 24 08:38:46 PM PDT 24	Jun 24 08:49:26 PM PDT 24	6304676240 ps
T55	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1561008709			Jun 24 08:13:04 PM PDT 24	Jun 24 09:24:06 PM PDT 24	15787391536 ps
T163	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3104270681			Jun 24 08:05:22 PM PDT 24	Jun 24 09:36:56 PM PDT 24	48360389736 ps
T389	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.188547245			Jun 24 08:29:02 PM PDT 24	Jun 24 08:35:31 PM PDT 24	3829722920 ps
T170	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.715633009			Jun 24 08:28:37 PM PDT 24	Jun 24 08:33:30 PM PDT 24	3495908058 ps
T284	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1222793874			Jun 24 08:06:28 PM PDT 24	Jun 24 08:12:11 PM PDT 24	4121992672 ps
T285	/workspace/coverage/default/2.chip_sw_aes_smoketest.1843111549			Jun 24 08:30:46 PM PDT 24	Jun 24 08:34:37 PM PDT 24	3470275000 ps
T209	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3715181965			Jun 24 08:13:42 PM PDT 24	Jun 24 08:23:55 PM PDT 24	5799400880 ps
T156	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117554042			Jun 24 08:39:20 PM PDT 24	Jun 24 08:45:51 PM PDT 24	3180009840 ps
T286	/workspace/coverage/default/0.chip_sw_csrng_kat_test.164005450			Jun 24 08:06:16 PM PDT 24	Jun 24 08:11:06 PM PDT 24	2706102266 ps
T232	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.528129774			Jun 24 08:31:20 PM PDT 24	Jun 24 08:42:09 PM PDT 24	5699348988 ps
T212	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2655814683			Jun 24 08:03:45 PM PDT 24	Jun 24 08:11:50 PM PDT 24	4820723136 ps
T27	/workspace/coverage/default/2.chip_sw_gpio.3708275404			Jun 24 08:20:56 PM PDT 24	Jun 24 08:29:19 PM PDT 24	4202104390 ps
T270	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4205732427			Jun 24 08:02:31 PM PDT 24	Jun 24 08:10:35 PM PDT 24	4975750340 ps
T271	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1674951464			Jun 24 08:16:35 PM PDT 24	Jun 24 08:22:43 PM PDT 24	3071096474 ps
T272	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.467870195			Jun 24 08:25:00 PM PDT 24	Jun 24 08:30:04 PM PDT 24	4027816152 ps
T273	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1703448704			Jun 24 08:08:17 PM PDT 24	Jun 24 08:26:29 PM PDT 24	8341007332 ps
T110	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3436159737			Jun 24 08:05:52 PM PDT 24	Jun 24 08:14:21 PM PDT 24	4534934589 ps
T274	/workspace/coverage/default/2.chip_sw_aes_entropy.2867270739			Jun 24 08:25:44 PM PDT 24	Jun 24 08:31:04 PM PDT 24	2791603132 ps
T235	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3108037495			Jun 24 08:16:07 PM PDT 24	Jun 24 08:23:17 PM PDT 24	4131549192 ps
T329	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.628488798			Jun 24 08:08:27 PM PDT 24	Jun 24 08:15:59 PM PDT 24	4270243350 ps
T824	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3127505795			Jun 24 08:07:18 PM PDT 24	Jun 24 08:16:03 PM PDT 24	4576478860 ps
T344	/workspace/coverage/default/95.chip_sw_all_escalation_resets.974880690			Jun 24 08:42:06 PM PDT 24	Jun 24 08:52:02 PM PDT 24	4667678736 ps
T825	/workspace/coverage/default/0.chip_sw_aes_enc.2686370541			Jun 24 08:03:48 PM PDT 24	Jun 24 08:08:27 PM PDT 24	2779637456 ps
T313	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2680212784			Jun 24 08:05:17 PM PDT 24	Jun 24 08:16:30 PM PDT 24	4528722994 ps
T121	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1771200320			Jun 24 08:23:12 PM PDT 24	Jun 24 08:56:49 PM PDT 24	9645000430 ps
T169	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1816923381			Jun 24 08:07:26 PM PDT 24	Jun 24 08:15:12 PM PDT 24	7953408480 ps
T390	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3130233459			Jun 24 08:07:08 PM PDT 24	Jun 24 08:18:59 PM PDT 24	5532562368 ps
T171	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1457935268			Jun 24 08:16:38 PM PDT 24	Jun 24 08:30:58 PM PDT 24	8809659227 ps
T396	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1232306313			Jun 24 08:11:47 PM PDT 24	Jun 24 09:15:09 PM PDT 24	12154041648 ps
T646	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157858295			Jun 24 08:36:57 PM PDT 24	Jun 24 08:43:35 PM PDT 24	4085630700 ps
T292	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1944130626			Jun 24 08:06:33 PM PDT 24	Jun 24 08:29:49 PM PDT 24	7897392600 ps
T205	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.841363653			Jun 24 08:22:39 PM PDT 24	Jun 24 08:49:04 PM PDT 24	9322732588 ps
T826	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2957228007			Jun 24 08:33:27 PM PDT 24	Jun 24 08:42:13 PM PDT 24	8199978262 ps
T607	/workspace/coverage/default/0.chip_sw_aes_masking_off.2040667351			Jun 24 08:05:33 PM PDT 24	Jun 24 08:12:19 PM PDT 24	2968309903 ps
T359	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193621035			Jun 24 08:37:49 PM PDT 24	Jun 24 08:44:26 PM PDT 24	4074847380 ps
T47	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3074518762			Jun 24 08:25:28 PM PDT 24	Jun 24 08:36:16 PM PDT 24	5162133352 ps
T142	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1183759578			Jun 24 08:33:06 PM PDT 24	Jun 24 09:03:26 PM PDT 24	13629056416 ps
T314	/workspace/coverage/default/2.chip_sw_hmac_enc.4140000472			Jun 24 08:27:08 PM PDT 24	Jun 24 08:31:37 PM PDT 24	2955498016 ps
T204	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1948852219			Jun 24 08:10:33 PM PDT 24	Jun 24 08:20:08 PM PDT 24	3481927074 ps
T365	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1969693084			Jun 24 08:08:54 PM PDT 24	Jun 24 08:15:02 PM PDT 24	6553594984 ps
T366	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2156226207			Jun 24 08:03:50 PM PDT 24	Jun 24 08:22:15 PM PDT 24	5802010660 ps
T249	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2281192419			Jun 24 08:05:00 PM PDT 24	Jun 24 08:06:47 PM PDT 24	2843857262 ps
T221	/workspace/coverage/default/2.rom_keymgr_functest.2335111339			Jun 24 08:29:48 PM PDT 24	Jun 24 08:41:28 PM PDT 24	4626653326 ps
T105	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2180935141			Jun 24 08:29:33 PM PDT 24	Jun 24 09:17:01 PM PDT 24	25097571359 ps
T213	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1004944559			Jun 24 08:36:16 PM PDT 24	Jun 24 08:43:55 PM PDT 24	3886459636 ps
T643	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2379655802			Jun 24 08:37:05 PM PDT 24	Jun 24 08:43:19 PM PDT 24	3584272498 ps
T206	/workspace/coverage/default/4.chip_tap_straps_prod.342449225			Jun 24 08:34:38 PM PDT 24	Jun 24 08:38:09 PM PDT 24	3277614433 ps
T609	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3416541703			Jun 24 08:24:45 PM PDT 24	Jun 24 08:47:27 PM PDT 24	7035668582 ps
T345	/workspace/coverage/default/36.chip_sw_all_escalation_resets.4290314831			Jun 24 08:37:20 PM PDT 24	Jun 24 08:47:26 PM PDT 24	5182510708 ps
T138	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3561322679			Jun 24 08:04:46 PM PDT 24	Jun 24 11:20:12 PM PDT 24	64967066544 ps
T115	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2851364508			Jun 24 08:28:32 PM PDT 24	Jun 24 08:40:01 PM PDT 24	4952755312 ps
T199	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1184697654			Jun 24 08:26:01 PM PDT 24	Jun 24 08:51:22 PM PDT 24	7256557880 ps
T210	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.499045351			Jun 24 08:23:17 PM PDT 24	Jun 24 08:44:42 PM PDT 24	8650521392 ps
T827	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1842564121			Jun 24 08:07:43 PM PDT 24	Jun 24 08:14:49 PM PDT 24	3309901694 ps
T319	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4211246237			Jun 24 08:32:23 PM PDT 24	Jun 24 08:57:13 PM PDT 24	8557438795 ps
T177	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3833690193			Jun 24 08:26:37 PM PDT 24	Jun 24 08:36:33 PM PDT 24	4925655738 ps
T828	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1174868095			Jun 24 08:05:29 PM PDT 24	Jun 24 08:09:00 PM PDT 24	2555213354 ps
T706	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3369251025			Jun 24 08:41:29 PM PDT 24	Jun 24 08:49:23 PM PDT 24	6095253504 ps
T397	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2662584121			Jun 24 08:12:41 PM PDT 24	Jun 24 09:30:58 PM PDT 24	15776477640 ps
T76	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3788620831			Jun 24 08:14:19 PM PDT 24	Jun 24 08:19:35 PM PDT 24	2686617663 ps
T63	/workspace/coverage/default/2.chip_tap_straps_rma.554889959			Jun 24 08:27:37 PM PDT 24	Jun 24 08:37:46 PM PDT 24	6980547775 ps
T398	/workspace/coverage/default/2.rom_e2e_asm_init_rma.2685910707			Jun 24 08:33:02 PM PDT 24	Jun 24 09:26:12 PM PDT 24	15611628715 ps
T829	/workspace/coverage/default/2.chip_sw_aon_timer_irq.1956036504			Jun 24 08:25:02 PM PDT 24	Jun 24 08:32:05 PM PDT 24	3965905072 ps
T400	/workspace/coverage/default/81.chip_sw_all_escalation_resets.1153379851			Jun 24 08:40:35 PM PDT 24	Jun 24 08:53:25 PM PDT 24	5210291418 ps
T830	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1619906306			Jun 24 08:05:23 PM PDT 24	Jun 24 08:11:39 PM PDT 24	4093594152 ps
T309	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3785528280			Jun 24 08:38:58 PM PDT 24	Jun 24 08:48:21 PM PDT 24	5251934484 ps
T831	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.515055453			Jun 24 08:23:44 PM PDT 24	Jun 24 08:31:34 PM PDT 24	6829325066 ps
T310	/workspace/coverage/default/2.chip_plic_all_irqs_20.2622193357			Jun 24 08:27:55 PM PDT 24	Jun 24 08:40:31 PM PDT 24	5076386960 ps
T640	/workspace/coverage/default/91.chip_sw_all_escalation_resets.272252776			Jun 24 08:40:45 PM PDT 24	Jun 24 08:51:37 PM PDT 24	4211805082 ps
T99	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.484238917			Jun 24 08:28:33 PM PDT 24	Jun 24 08:38:17 PM PDT 24	18658566916 ps
T322	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.463726822			Jun 24 08:02:24 PM PDT 24	Jun 24 08:13:23 PM PDT 24	5278096700 ps
T24	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4092810314			Jun 24 08:06:18 PM PDT 24	Jun 24 08:17:54 PM PDT 24	5565841533 ps
T704	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2990380955			Jun 24 08:39:47 PM PDT 24	Jun 24 08:48:55 PM PDT 24	6250252002 ps
T56	/workspace/coverage/default/2.chip_sw_alert_test.1535212481			Jun 24 08:25:07 PM PDT 24	Jun 24 08:31:43 PM PDT 24	3518494584 ps
T164	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1076392088			Jun 24 08:03:23 PM PDT 24	Jun 24 08:05:46 PM PDT 24	3435243682 ps
T401	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2498923412			Jun 24 08:09:43 PM PDT 24	Jun 24 08:15:02 PM PDT 24	2758213730 ps
T25	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1570411026			Jun 24 08:11:43 PM PDT 24	Jun 24 08:21:22 PM PDT 24	5828895104 ps
T233	/workspace/coverage/default/56.chip_sw_all_escalation_resets.236541265			Jun 24 08:39:27 PM PDT 24	Jun 24 08:48:06 PM PDT 24	5692859986 ps
T427	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3188780291			Jun 24 08:24:29 PM PDT 24	Jun 24 08:48:25 PM PDT 24	8604150704 ps
T211	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.834349773			Jun 24 08:16:55 PM PDT 24	Jun 24 09:21:42 PM PDT 24	15678573400 ps
T832	/workspace/coverage/default/0.rom_keymgr_functest.1459420283			Jun 24 08:06:59 PM PDT 24	Jun 24 08:17:12 PM PDT 24	5551442148 ps
T294	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2108777015			Jun 24 08:42:24 PM PDT 24	Jun 24 08:48:18 PM PDT 24	3754160144 ps
T833	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.290452041			Jun 24 08:22:55 PM PDT 24	Jun 24 08:28:36 PM PDT 24	4039708888 ps
T30	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1833032367			Jun 24 08:04:26 PM PDT 24	Jun 24 09:57:11 PM PDT 24	31691827900 ps
T133	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2831382465			Jun 24 08:32:44 PM PDT 24	Jun 24 08:41:13 PM PDT 24	3724107728 ps
T834	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2842511208			Jun 24 08:05:24 PM PDT 24	Jun 24 08:15:01 PM PDT 24	4965101884 ps
T835	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1100771323			Jun 24 08:19:49 PM PDT 24	Jun 24 08:25:15 PM PDT 24	2403449694 ps
T836	/workspace/coverage/default/1.rom_keymgr_functest.1833888419			Jun 24 08:22:06 PM PDT 24	Jun 24 08:32:13 PM PDT 24	5825493770 ps
T367	/workspace/coverage/default/2.rom_e2e_asm_init_dev.2898326537			Jun 24 08:34:59 PM PDT 24	Jun 24 09:30:21 PM PDT 24	15783803282 ps
T709	/workspace/coverage/default/72.chip_sw_all_escalation_resets.1830837657			Jun 24 08:41:58 PM PDT 24	Jun 24 08:53:23 PM PDT 24	5724325106 ps
T664	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3467889258			Jun 24 08:02:29 PM PDT 24	Jun 24 08:13:58 PM PDT 24	5582448296 ps
T837	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3891974753			Jun 24 08:32:16 PM PDT 24	Jun 24 08:37:49 PM PDT 24	2716857896 ps
T420	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2309504887			Jun 24 08:38:18 PM PDT 24	Jun 24 08:44:46 PM PDT 24	3762726944 ps
T610	/workspace/coverage/default/0.chip_sw_edn_sw_mode.3845804183			Jun 24 08:04:25 PM PDT 24	Jun 24 08:47:28 PM PDT 24	9835727466 ps
T667	/workspace/coverage/default/82.chip_sw_all_escalation_resets.569309515			Jun 24 08:42:10 PM PDT 24	Jun 24 08:50:43 PM PDT 24	5859344882 ps
T100	/workspace/coverage/default/2.chip_sw_power_sleep_load.3994268717			Jun 24 08:29:38 PM PDT 24	Jun 24 08:37:16 PM PDT 24	4261980190 ps
T838	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4147918684			Jun 24 08:04:41 PM PDT 24	Jun 24 08:15:04 PM PDT 24	7747936670 ps
T71	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2650984656			Jun 24 08:09:08 PM PDT 24	Jun 24 08:45:23 PM PDT 24	24955078123 ps
T839	/workspace/coverage/default/0.chip_sw_example_concurrency.118110508			Jun 24 08:02:38 PM PDT 24	Jun 24 08:06:11 PM PDT 24	2874638632 ps
T346	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2648917754			Jun 24 08:36:24 PM PDT 24	Jun 24 08:47:31 PM PDT 24	5763267804 ps
T840	/workspace/coverage/default/1.chip_sw_aes_smoketest.2508438885			Jun 24 08:22:32 PM PDT 24	Jun 24 08:27:57 PM PDT 24	3098401052 ps
T347	/workspace/coverage/default/80.chip_sw_all_escalation_resets.2990373219			Jun 24 08:41:07 PM PDT 24	Jun 24 08:51:22 PM PDT 24	6224449296 ps
T28	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2936914701			Jun 24 08:37:07 PM PDT 24	Jun 24 08:58:59 PM PDT 24	8456543368 ps
T386	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.835517779			Jun 24 08:28:52 PM PDT 24	Jun 24 08:31:36 PM PDT 24	2188302784 ps
T387	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4018265982			Jun 24 08:18:58 PM PDT 24	Jun 24 08:24:24 PM PDT 24	3538043244 ps
T642	/workspace/coverage/default/29.chip_sw_all_escalation_resets.811897191			Jun 24 08:38:30 PM PDT 24	Jun 24 08:49:20 PM PDT 24	4714117492 ps
T66	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3207401856			Jun 24 08:31:35 PM PDT 24	Jun 24 08:35:36 PM PDT 24	2791973793 ps
T674	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.793954177			Jun 24 08:40:20 PM PDT 24	Jun 24 08:47:05 PM PDT 24	3992624520 ps
T655	/workspace/coverage/default/67.chip_sw_all_escalation_resets.2350447555			Jun 24 08:39:49 PM PDT 24	Jun 24 08:52:07 PM PDT 24	4926244150 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4253269589			Jun 24 08:03:51 PM PDT 24	Jun 24 08:12:41 PM PDT 24	4858798600 ps
T33	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3234000097			Jun 24 08:22:34 PM PDT 24	Jun 24 09:15:33 PM PDT 24	20225600050 ps
T368	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1100911935			Jun 24 08:12:10 PM PDT 24	Jun 24 09:25:08 PM PDT 24	15193100314 ps
T168	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1079456486			Jun 24 08:10:16 PM PDT 24	Jun 24 08:28:22 PM PDT 24	8099375392 ps
T191	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.66845610			Jun 24 08:22:49 PM PDT 24	Jun 24 11:33:22 PM PDT 24	64520201907 ps
T21	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.349347985			Jun 24 08:10:59 PM PDT 24	Jun 24 08:16:55 PM PDT 24	2679562362 ps
T841	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3275511092			Jun 24 08:20:55 PM PDT 24	Jun 24 08:39:15 PM PDT 24	5977752623 ps
T842	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.904295347			Jun 24 08:31:16 PM PDT 24	Jun 24 08:39:38 PM PDT 24	7231154879 ps
T843	/workspace/coverage/default/0.rom_e2e_static_critical.3851698037			Jun 24 08:11:07 PM PDT 24	Jun 24 09:20:35 PM PDT 24	18054070526 ps
T844	/workspace/coverage/default/0.chip_sw_csrng_smoketest.3788433969			Jun 24 08:08:36 PM PDT 24	Jun 24 08:12:42 PM PDT 24	2862177824 ps
T721	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2435629205			Jun 24 08:37:46 PM PDT 24	Jun 24 08:43:39 PM PDT 24	4015392252 ps
T215	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.402525316			Jun 24 08:05:11 PM PDT 24	Jun 24 08:13:40 PM PDT 24	5625891672 ps
T214	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.743576393			Jun 24 08:06:44 PM PDT 24	Jun 24 09:29:59 PM PDT 24	15888371600 ps
T101	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4188568013			Jun 24 08:05:51 PM PDT 24	Jun 24 08:16:14 PM PDT 24	19187618760 ps
T641	/workspace/coverage/default/1.chip_sw_hmac_multistream.1391434797			Jun 24 08:13:59 PM PDT 24	Jun 24 08:42:31 PM PDT 24	6953358340 ps
T845	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1841036753			Jun 24 08:13:28 PM PDT 24	Jun 24 08:17:26 PM PDT 24	3096578360 ps
T111	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3041406547			Jun 24 08:18:03 PM PDT 24	Jun 24 08:28:45 PM PDT 24	5772383628 ps
T119	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1672980024			Jun 24 08:06:25 PM PDT 24	Jun 24 08:16:42 PM PDT 24	5992794417 ps
T241	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2814889781			Jun 24 08:13:21 PM PDT 24	Jun 24 09:01:13 PM PDT 24	24206173609 ps
T846	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1008152726			Jun 24 08:10:05 PM PDT 24	Jun 24 08:14:02 PM PDT 24	2083313896 ps
T661	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1425016270			Jun 24 08:40:12 PM PDT 24	Jun 24 08:47:27 PM PDT 24	3801558220 ps
T668	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.377017705			Jun 24 08:37:33 PM PDT 24	Jun 24 08:43:19 PM PDT 24	3409846324 ps
T236	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082991681			Jun 24 08:37:35 PM PDT 24	Jun 24 08:42:40 PM PDT 24	3643200400 ps
T145	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.594853627			Jun 24 08:28:13 PM PDT 24	Jun 24 09:21:05 PM PDT 24	17419144600 ps
T72	/workspace/coverage/default/1.chip_jtag_mem_access.3915470913			Jun 24 08:10:17 PM PDT 24	Jun 24 08:34:27 PM PDT 24	13016000408 ps
T275	/workspace/coverage/default/5.chip_sw_all_escalation_resets.365347635			Jun 24 08:36:42 PM PDT 24	Jun 24 08:45:55 PM PDT 24	4290185402 ps
T276	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1670935604			Jun 24 08:36:42 PM PDT 24	Jun 24 08:44:03 PM PDT 24	3604506720 ps
T277	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.854644076			Jun 24 08:26:05 PM PDT 24	Jun 24 08:41:50 PM PDT 24	4590288000 ps
T278	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3636956997			Jun 24 08:36:28 PM PDT 24	Jun 24 08:45:46 PM PDT 24	7692892570 ps
T279	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4100174784			Jun 24 08:02:53 PM PDT 24	Jun 24 08:25:26 PM PDT 24	9718255770 ps
T280	/workspace/coverage/default/68.chip_sw_all_escalation_resets.32448354			Jun 24 08:38:56 PM PDT 24	Jun 24 08:48:00 PM PDT 24	4342189112 ps
T84	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2956003772			Jun 24 08:36:29 PM PDT 24	Jun 24 08:42:20 PM PDT 24	3726086992 ps
T391	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1118411666			Jun 24 08:04:36 PM PDT 24	Jun 24 08:30:35 PM PDT 24	6599629896 ps
T193	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4046527101			Jun 24 08:04:27 PM PDT 24	Jun 24 08:09:58 PM PDT 24	3339571438 ps
T295	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4175097079			Jun 24 08:37:12 PM PDT 24	Jun 24 08:45:46 PM PDT 24	3652951230 ps
T302	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.931378671			Jun 24 08:35:35 PM PDT 24	Jun 24 08:42:08 PM PDT 24	4198048000 ps
T253	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2224538845			Jun 24 08:27:11 PM PDT 24	Jun 24 08:35:45 PM PDT 24	9482970409 ps
T303	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.712295493			Jun 24 08:03:11 PM PDT 24	Jun 24 08:31:34 PM PDT 24	9538968168 ps
T304	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2033198602			Jun 24 08:37:45 PM PDT 24	Jun 24 08:43:36 PM PDT 24	3758967040 ps
T305	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2437684391			Jun 24 08:36:35 PM PDT 24	Jun 24 08:47:19 PM PDT 24	5819755800 ps
T306	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4059928897			Jun 24 08:25:37 PM PDT 24	Jun 24 08:31:25 PM PDT 24	3574629412 ps
T307	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4118463115			Jun 24 08:38:52 PM PDT 24	Jun 24 08:46:16 PM PDT 24	3463905110 ps
T308	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.375236880			Jun 24 08:39:30 PM PDT 24	Jun 24 08:45:34 PM PDT 24	3677839350 ps
T150	/workspace/coverage/default/1.chip_plic_all_irqs_10.2232429485			Jun 24 08:15:58 PM PDT 24	Jun 24 08:26:21 PM PDT 24	4483232824 ps
T165	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.33791740			Jun 24 08:06:06 PM PDT 24	Jun 24 08:52:31 PM PDT 24	34433273376 ps
T847	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4189956683			Jun 24 08:24:48 PM PDT 24	Jun 24 08:29:49 PM PDT 24	2497374933 ps
T226	/workspace/coverage/default/1.chip_sw_flash_init.803330068			Jun 24 08:09:28 PM PDT 24	Jun 24 08:44:49 PM PDT 24	26772387248 ps
T648	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3939780314			Jun 24 08:22:34 PM PDT 24	Jun 24 08:45:09 PM PDT 24	11390756497 ps
T848	/workspace/coverage/default/2.chip_sw_uart_tx_rx.148618100			Jun 24 08:22:43 PM PDT 24	Jun 24 08:33:57 PM PDT 24	4289892368 ps
T31	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.148792046			Jun 24 08:30:48 PM PDT 24	Jun 24 08:37:33 PM PDT 24	5694061720 ps
T849	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2528351392			Jun 24 08:06:04 PM PDT 24	Jun 24 08:16:58 PM PDT 24	5667426340 ps
T850	/workspace/coverage/default/2.chip_tap_straps_dev.2845602674			Jun 24 08:29:10 PM PDT 24	Jun 24 08:49:27 PM PDT 24	10158560649 ps
T172	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1991298847			Jun 24 08:22:24 PM PDT 24	Jun 24 08:27:11 PM PDT 24	3050324917 ps
T684	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.481608751			Jun 24 08:39:15 PM PDT 24	Jun 24 08:46:06 PM PDT 24	4033161640 ps
T851	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3689874947			Jun 24 08:11:00 PM PDT 24	Jun 24 09:14:16 PM PDT 24	15688615764 ps
T216	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1019210084			Jun 24 08:19:37 PM PDT 24	Jun 24 08:46:20 PM PDT 24	9031300752 ps
T7	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2083003446			Jun 24 08:06:46 PM PDT 24	Jun 24 08:12:37 PM PDT 24	3916953192 ps
T852	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2556907337			Jun 24 08:27:35 PM PDT 24	Jun 24 08:45:26 PM PDT 24	10387520351 ps
T77	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.183232716			Jun 24 08:05:11 PM PDT 24	Jun 24 08:37:30 PM PDT 24	11512956756 ps
T853	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3285160969			Jun 24 08:11:41 PM PDT 24	Jun 24 08:36:22 PM PDT 24	9890618437 ps
T854	/workspace/coverage/default/0.chip_sw_aes_entropy.2926638973			Jun 24 08:04:55 PM PDT 24	Jun 24 08:09:43 PM PDT 24	2707716004 ps
T194	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2327955059			Jun 24 08:12:45 PM PDT 24	Jun 24 08:26:08 PM PDT 24	4554100483 ps
T422	/workspace/coverage/default/1.chip_sw_kmac_entropy.2647690565			Jun 24 08:09:42 PM PDT 24	Jun 24 08:15:25 PM PDT 24	3164912400 ps
T291	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3682203260			Jun 24 08:41:06 PM PDT 24	Jun 24 08:50:35 PM PDT 24	5278932454 ps
T124	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.618678052			Jun 24 08:16:20 PM PDT 24	Jun 24 08:25:09 PM PDT 24	5448950542 ps
T855	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3637377236			Jun 24 08:11:50 PM PDT 24	Jun 24 08:25:38 PM PDT 24	7913095070 ps
T669	/workspace/coverage/default/48.chip_sw_all_escalation_resets.1037978523			Jun 24 08:38:55 PM PDT 24	Jun 24 08:51:46 PM PDT 24	5261087912 ps
T856	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.846989726			Jun 24 08:28:12 PM PDT 24	Jun 24 09:24:31 PM PDT 24	15362477148 ps
T647	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3442888258			Jun 24 08:37:10 PM PDT 24	Jun 24 08:43:29 PM PDT 24	3595735132 ps
T857	/workspace/coverage/default/2.chip_sw_csrng_kat_test.2805995619			Jun 24 08:25:09 PM PDT 24	Jun 24 08:29:42 PM PDT 24	2901985016 ps
T102	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1345548931			Jun 24 08:29:34 PM PDT 24	Jun 24 09:07:45 PM PDT 24	17092062464 ps
T858	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2896510710			Jun 24 08:16:35 PM PDT 24	Jun 24 08:27:23 PM PDT 24	4620751630 ps
T859	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.783316620			Jun 24 08:08:02 PM PDT 24	Jun 24 08:17:29 PM PDT 24	4611306084 ps
T860	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2934754943			Jun 24 08:04:46 PM PDT 24	Jun 24 08:20:54 PM PDT 24	8099445546 ps
T57	/workspace/coverage/default/0.chip_sw_alert_test.1391827244			Jun 24 08:05:05 PM PDT 24	Jun 24 08:10:16 PM PDT 24	3599587530 ps
T148	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.853856664			Jun 24 08:21:58 PM PDT 24	Jun 24 11:26:43 PM PDT 24	59189355003 ps
T135	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2237640592			Jun 24 08:03:06 PM PDT 24	Jun 24 08:11:59 PM PDT 24	7934219935 ps
T143	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2836444476			Jun 24 08:21:46 PM PDT 24	Jun 24 08:40:13 PM PDT 24	8494011156 ps
T333	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.127353616			Jun 24 08:29:20 PM PDT 24	Jun 24 08:33:20 PM PDT 24	3607302633 ps
T735	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2982329426			Jun 24 08:08:56 PM PDT 24	Jun 24 08:20:39 PM PDT 24	6031130544 ps
T861	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2773670834			Jun 24 08:23:49 PM PDT 24	Jun 24 09:07:47 PM PDT 24	27821551443 ps
T166	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.128368781			Jun 24 08:22:40 PM PDT 24	Jun 24 08:26:02 PM PDT 24	3672866438 ps
T677	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2311611570			Jun 24 08:37:00 PM PDT 24	Jun 24 08:47:51 PM PDT 24	5921058048 ps
T79	/workspace/coverage/default/0.chip_sw_usbdev_vbus.531685727			Jun 24 08:04:21 PM PDT 24	Jun 24 08:08:21 PM PDT 24	2801157836 ps
T244	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.156296575			Jun 24 08:06:09 PM PDT 24	Jun 24 08:24:08 PM PDT 24	7267122916 ps
T242	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.987821971			Jun 24 08:05:37 PM PDT 24	Jun 24 08:37:02 PM PDT 24	27436244509 ps
T862	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.410109905			Jun 24 08:12:23 PM PDT 24	Jun 24 08:17:20 PM PDT 24	3554371300 ps
T203	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3376893315			Jun 24 08:38:25 PM PDT 24	Jun 24 08:47:28 PM PDT 24	3821580932 ps