Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	163092	1			T68	4		T73	29		T122	4
values[2]	4711	1			T73	1		T379	1		T425	7
values[3]	2188	1			T514	22		T619	20		T541	60
values[4]	1750	1			T514	24		T619	27		T541	14
values[5]	1270	1			T514	11		T619	43		T541	5
values[6]	1027	1			T514	3		T619	63		T541	7
values[7]	844	1			T619	58		T541	14		T762	2
values[8]	740	1			T619	49		T541	1		T762	2
values[9]	641	1			T619	44		T762	2		T409	1
values[10]	558	1			T619	23		T762	2		T781	7
values[11]	487	1			T619	22		T762	2		T781	10
values[12]	453	1			T619	32		T762	2		T781	13
values[13]	464	1			T619	18		T762	2		T781	7
values[14]	422	1			T619	14		T762	2		T781	2
values[15]	353	1			T619	17		T762	2		T781	11
values[16]	276	1			T619	8		T762	2		T781	3
values[17]	264	1			T619	7		T762	2		T781	4
values[18]	257	1			T762	2		T781	2		T763	2
values[19]	227	1			T762	2		T781	3		T763	2
values[20]	221	1			T762	2		T781	3		T763	2
values[21]	232	1			T762	2		T781	4		T763	2
values[22]	216	1			T762	2		T781	1		T763	2
values[23]	166	1			T762	2		T781	4		T763	2
values[24]	161	1			T762	2		T781	2		T763	2
values[25]	133	1			T762	2		T781	3		T763	2
values[26]	122	1			T762	2		T781	6		T763	2
values[27]	132	1			T762	2		T781	11		T763	2
values[28]	123	1			T762	2		T781	14		T763	2
values[29]	105	1			T762	2		T781	12		T763	2
values[30]	74	1			T762	2		T781	4		T763	2
values[31]	85	1			T762	2		T781	1		T763	2
values[32]	88	1			T762	2		T781	4		T763	2
values[33]	105	1			T762	2		T781	6		T763	2
values[34]	102	1			T762	2		T781	5		T763	2
values[35]	74	1			T762	2		T781	3		T763	2
values[36]	81	1			T762	2		T781	3		T763	2
values[37]	73	1			T762	2		T781	4		T763	2
values[38]	63	1			T762	2		T781	1		T763	2
values[39]	60	1			T762	2		T763	2		T782	1
values[40]	55	1			T762	2		T763	2		T782	1
values[41]	68	1			T762	2		T763	2		T782	1
values[42]	74	1			T762	2		T763	2		T782	1
values[43]	84	1			T762	2		T763	2		T782	1
values[44]	73	1			T762	2		T763	2		T782	1
values[45]	73	1			T762	2		T763	2		T782	1
values[46]	78	1			T762	2		T763	2		T782	1
values[47]	74	1			T762	2		T763	2		T782	1
values[48]	52	1			T762	2		T763	2		T782	1
values[49]	47	1			T762	2		T763	2		T782	1
values[50]	60	1			T762	2		T763	2		T782	1
values[51]	68	1			T762	2		T763	2		T782	1
values[52]	51	1			T762	2		T763	2		T782	1
values[53]	48	1			T762	2		T763	2		T782	1
values[54]	47	1			T762	2		T763	2		T782	1
values[55]	42	1			T762	2		T763	2		T782	1
values[56]	53	1			T762	2		T763	2		T782	1
values[57]	45	1			T762	2		T763	2		T782	1
values[58]	47	1			T762	2		T763	2		T782	1
values[59]	44	1			T762	2		T763	2		T782	1
values[60]	50	1			T762	2		T763	2		T782	1
values[61]	45	1			T762	3		T763	2		T782	1
values[62]	39	1			T762	2		T763	2		T782	1
values[63]	38	1			T762	2		T763	2		T782	1
values[64]	43	1			T762	2		T763	2		T782	1
values[65]	42	1			T762	2		T763	2		T782	1
values[66]	47	1			T762	2		T763	2		T782	1
values[67]	48	1			T762	2		T763	2		T782	1
values[68]	48	1			T762	2		T763	2		T782	1
values[69]	47	1			T762	2		T763	2		T782	1
values[70]	49	1			T762	2		T763	2		T782	1
values[71]	53	1			T762	2		T763	2		T782	1
values[72]	47	1			T762	2		T763	2		T782	1
values[73]	53	1			T762	2		T763	2		T782	1
values[74]	50	1			T762	2		T763	2		T782	1
values[75]	44	1			T762	2		T763	2		T782	2
values[76]	58	1			T762	2		T763	2		T782	1
values[77]	54	1			T762	2		T763	2		T782	1
values[78]	49	1			T762	5		T763	2		T782	1
values[79]	67	1			T762	12		T763	11		T782	1
values[80]	77	1			T762	12		T763	13		T782	1
values[81]	60	1			T762	5		T763	6		T782	1
values[82]	50	1			T762	5		T763	4		T782	1
values[83]	56	1			T762	5		T763	2		T782	1
values[84]	55	1			T762	3		T763	5		T782	1
values[85]	55	1			T762	2		T763	8		T782	1
values[86]	64	1			T762	5		T763	6		T782	1
values[87]	51	1			T762	4		T763	3		T782	1
values[88]	54	1			T762	3		T763	3		T782	1
values[89]	58	1			T762	5		T763	4		T782	1
values[90]	66	1			T762	3		T763	5		T782	1
values[91]	69	1			T762	2		T763	3		T782	1
values[92]	72	1			T762	3		T763	6		T782	1
values[93]	69	1			T762	3		T763	6		T782	1
values[94]	68	1			T762	3		T763	12		T782	1
values[95]	90	1			T762	3		T763	4		T782	1
values[96]	94	1			T762	2		T763	3		T782	1
values[97]	74	1			T762	3		T763	7		T782	1
values[98]	85	1			T762	4		T763	3		T782	1
values[99]	75	1			T762	3		T763	6		T782	1
values[100]	78	1			T762	3		T763	4		T782	1
values[101]	70	1			T762	3		T763	7		T782	1
values[102]	71	1			T762	2		T763	5		T782	1
values[103]	77	1			T762	3		T763	5		T782	1
values[104]	75	1			T762	3		T763	7		T782	1
values[105]	88	1			T762	2		T763	5		T782	1
values[106]	80	1			T762	3		T763	7		T782	1
values[107]	67	1			T762	5		T763	3		T782	1
values[108]	74	1			T762	2		T763	4		T782	1
values[109]	64	1			T762	3		T763	3		T782	1
values[110]	76	1			T762	3		T763	6		T782	1
values[111]	75	1			T762	5		T763	4		T782	1
values[112]	63	1			T762	5		T763	3		T782	1
values[113]	76	1			T762	3		T763	3		T782	1
values[114]	88	1			T762	2		T763	5		T782	2
values[115]	80	1			T762	2		T763	4		T782	2
values[116]	85	1			T762	5		T763	5		T782	5
values[117]	87	1			T762	3		T763	4		T782	3
values[118]	90	1			T762	2		T763	2		T782	9
values[119]	77	1			T762	5		T763	4		T782	2
values[120]	86	1			T762	2		T763	5		T782	3
values[121]	80	1			T762	2		T763	3		T782	2
values[122]	94	1			T762	2		T763	5		T782	3
values[123]	122	1			T762	4		T763	5		T782	3
values[124]	223	1			T762	2		T763	7		T782	3
values[125]	313	1			T762	3		T763	6		T782	2
values[126]	637	1			T762	31		T763	21		T782	17
values[127]	2736	1			T762	222		T763	191		T782	110
values[128]	5068	1			T762	414		T763	387		T782	220