Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	148485	1			T68	4		T70	6		T73	18
values[2]	12044	1			T73	1		T379	3		T237	2
values[3]	4552	1			T514	10		T405	44		T541	43
values[4]	2562	1			T514	10		T405	30		T541	21
values[5]	1766	1			T514	11		T405	37		T541	23
values[6]	1176	1			T514	1		T405	20		T541	20
values[7]	759	1			T514	2		T405	23		T541	13
values[8]	531	1			T514	1		T405	8		T541	3
values[9]	380	1			T405	13		T541	2		T554	10
values[10]	372	1			T405	14		T541	2		T554	13
values[11]	355	1			T405	7		T541	4		T554	11
values[12]	397	1			T405	11		T541	6		T554	11
values[13]	326	1			T405	15		T541	2		T554	7
values[14]	327	1			T405	2		T541	3		T554	7
values[15]	311	1			T405	4		T541	2		T554	4
values[16]	338	1			T405	14		T541	2		T554	9
values[17]	329	1			T405	10		T541	3		T554	7
values[18]	290	1			T405	3		T541	1		T554	13
values[19]	302	1			T405	4		T554	5		T758	15
values[20]	286	1			T405	4		T554	6		T758	11
values[21]	340	1			T405	4		T554	9		T758	12
values[22]	292	1			T405	2		T554	29		T758	15
values[23]	333	1			T405	4		T554	6		T758	16
values[24]	325	1			T405	4		T554	8		T758	31
values[25]	320	1			T405	2		T554	6		T758	26
values[26]	317	1			T405	2		T554	4		T758	8
values[27]	311	1			T405	5		T554	5		T758	11
values[28]	296	1			T405	2		T554	8		T758	7
values[29]	320	1			T405	1		T554	4		T758	7
values[30]	334	1			T405	2		T554	9		T758	31
values[31]	283	1			T405	5		T554	6		T758	17
values[32]	284	1			T405	2		T554	9		T758	12
values[33]	303	1			T405	1		T554	13		T758	18
values[34]	306	1			T405	1		T554	11		T758	8
values[35]	325	1			T405	1		T554	7		T758	7
values[36]	318	1			T405	2		T554	7		T758	25
values[37]	288	1			T405	3		T554	11		T758	13
values[38]	293	1			T405	1		T554	9		T758	11
values[39]	313	1			T405	3		T554	9		T758	35
values[40]	268	1			T405	5		T554	5		T758	12
values[41]	274	1			T405	12		T554	7		T758	10
values[42]	306	1			T405	8		T554	9		T758	17
values[43]	257	1			T405	6		T554	5		T758	12
values[44]	270	1			T405	3		T554	11		T758	13
values[45]	311	1			T405	6		T554	5		T758	11
values[46]	261	1			T405	4		T554	3		T758	13
values[47]	251	1			T405	2		T554	6		T758	18
values[48]	247	1			T405	1		T554	4		T758	7
values[49]	282	1			T405	2		T554	8		T758	6
values[50]	248	1			T405	1		T554	6		T758	10
values[51]	252	1			T405	2		T554	13		T758	18
values[52]	320	1			T405	4		T554	5		T758	11
values[53]	257	1			T405	4		T554	4		T758	16
values[54]	255	1			T405	2		T554	7		T758	28
values[55]	225	1			T405	2		T554	5		T758	25
values[56]	219	1			T405	1		T554	7		T758	20
values[57]	235	1			T405	1		T554	18		T758	16
values[58]	252	1			T405	6		T554	3		T758	26
values[59]	197	1			T405	7		T554	12		T758	11
values[60]	220	1			T405	7		T554	17		T758	14
values[61]	194	1			T405	10		T554	9		T758	17
values[62]	168	1			T405	5		T554	8		T758	8
values[63]	157	1			T405	4		T554	1		T758	9
values[64]	187	1			T405	3		T758	16		T412	3
values[65]	188	1			T405	2		T758	18		T412	10
values[66]	217	1			T405	1		T758	20		T412	7
values[67]	224	1			T405	3		T758	28		T412	6
values[68]	163	1			T405	2		T758	15		T412	4
values[69]	167	1			T405	3		T758	7		T412	20
values[70]	146	1			T405	5		T758	10		T412	7
values[71]	128	1			T405	3		T758	8		T412	8
values[72]	124	1			T405	2		T758	10		T412	7
values[73]	130	1			T405	2		T758	6		T412	7
values[74]	111	1			T405	6		T758	2		T412	2
values[75]	119	1			T405	10		T412	10		T778	1
values[76]	91	1			T405	9		T412	3		T778	1
values[77]	88	1			T405	3		T412	5		T778	1
values[78]	85	1			T405	5		T412	4		T778	1
values[79]	91	1			T405	10		T412	11		T778	1
values[80]	80	1			T405	7		T412	2		T778	1
values[81]	85	1			T405	6		T778	1		T766	1
values[82]	91	1			T405	7		T778	1		T766	1
values[83]	117	1			T405	10		T778	1		T766	1
values[84]	80	1			T405	8		T778	1		T766	1
values[85]	60	1			T405	5		T778	1		T766	1
values[86]	93	1			T405	8		T778	1		T766	1
values[87]	83	1			T405	7		T778	1		T766	1
values[88]	83	1			T405	15		T778	1		T766	1
values[89]	84	1			T405	13		T778	1		T766	1
values[90]	87	1			T405	12		T778	1		T766	1
values[91]	71	1			T405	10		T778	1		T766	1
values[92]	80	1			T405	7		T778	1		T766	1
values[93]	66	1			T405	4		T778	1		T766	1
values[94]	75	1			T405	3		T778	1		T766	1
values[95]	78	1			T405	7		T778	1		T766	1
values[96]	63	1			T405	7		T778	1		T766	1
values[97]	64	1			T405	5		T778	1		T766	2
values[98]	69	1			T405	4		T778	1		T766	1
values[99]	73	1			T405	8		T778	1		T766	1
values[100]	67	1			T405	7		T778	1		T766	1
values[101]	65	1			T405	3		T778	1		T766	1
values[102]	87	1			T405	4		T778	1		T766	1
values[103]	79	1			T405	7		T778	1		T766	1
values[104]	59	1			T405	9		T778	1		T766	1
values[105]	97	1			T405	6		T778	1		T766	12
values[106]	75	1			T405	6		T778	1		T766	4
values[107]	51	1			T405	5		T778	1		T766	2
values[108]	65	1			T405	4		T778	1		T766	3
values[109]	56	1			T405	10		T778	1		T766	1
values[110]	89	1			T405	6		T778	1		T766	3
values[111]	82	1			T405	1		T778	1		T766	3
values[112]	71	1			T778	1		T766	2		T533	1
values[113]	63	1			T778	3		T766	1		T533	2
values[114]	49	1			T778	1		T766	1		T533	1
values[115]	47	1			T778	1		T766	2		T533	1
values[116]	63	1			T778	1		T766	1		T533	2
values[117]	55	1			T778	1		T766	4		T533	8
values[118]	46	1			T778	1		T766	1		T533	1
values[119]	61	1			T778	1		T766	1		T533	1
values[120]	58	1			T778	1		T766	5		T533	1
values[121]	46	1			T778	2		T766	2		T533	1
values[122]	54	1			T778	2		T766	2		T533	3
values[123]	53	1			T778	1		T766	3		T533	2
values[124]	46	1			T778	1		T766	1		T533	2
values[125]	58	1			T778	1		T766	1		T533	1
values[126]	115	1			T778	7		T766	2		T533	4
values[127]	758	1			T778	21		T766	29		T533	27
values[128]	6951	1			T778	262		T766	278		T533	380