Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144054	1			T68	4		T70	4		T73	22
values[2]	7704	1			T73	2		T74	9		T379	2
values[3]	3507	1			T74	9		T554	58		T649	8
values[4]	2237	1			T74	11		T554	32		T649	16
values[5]	1510	1			T74	9		T554	30		T649	5
values[6]	1002	1			T74	7		T554	26		T649	9
values[7]	901	1			T74	9		T554	41		T649	4
values[8]	693	1			T74	7		T554	13		T758	15
values[9]	651	1			T74	16		T554	7		T758	13
values[10]	623	1			T74	19		T554	14		T758	8
values[11]	582	1			T74	12		T554	3		T758	7
values[12]	531	1			T74	11		T554	7		T758	8
values[13]	556	1			T74	15		T554	16		T758	6
values[14]	538	1			T74	11		T554	23		T758	7
values[15]	485	1			T74	6		T554	5		T758	11
values[16]	513	1			T74	4		T554	13		T758	19
values[17]	495	1			T74	6		T554	11		T758	5
values[18]	394	1			T74	11		T554	7		T758	3
values[19]	430	1			T74	9		T554	16		T758	5
values[20]	481	1			T74	10		T554	14		T758	8
values[21]	430	1			T74	11		T554	8		T758	16
values[22]	390	1			T74	5		T554	10		T758	16
values[23]	372	1			T74	5		T554	13		T758	8
values[24]	404	1			T74	3		T758	13		T411	16
values[25]	376	1			T74	9		T758	7		T411	12
values[26]	405	1			T74	10		T758	8		T411	14
values[27]	370	1			T74	12		T758	5		T411	11
values[28]	338	1			T74	5		T758	6		T411	11
values[29]	336	1			T74	9		T758	12		T411	5
values[30]	350	1			T74	14		T758	4		T411	7
values[31]	341	1			T74	15		T758	9		T411	6
values[32]	348	1			T74	13		T758	27		T411	12
values[33]	385	1			T74	5		T758	5		T411	5
values[34]	295	1			T74	3		T758	4		T411	9
values[35]	337	1			T74	3		T758	7		T411	16
values[36]	398	1			T74	6		T758	7		T411	4
values[37]	370	1			T74	12		T758	3		T411	22
values[38]	367	1			T74	4		T758	16		T411	7
values[39]	331	1			T74	11		T758	4		T411	12
values[40]	381	1			T74	13		T758	13		T411	12
values[41]	281	1			T74	6		T758	9		T411	3
values[42]	260	1			T74	8		T758	7		T411	15
values[43]	255	1			T74	5		T758	7		T411	10
values[44]	305	1			T74	9		T758	22		T411	8
values[45]	181	1			T74	5		T758	6		T762	1
values[46]	186	1			T74	3		T758	9		T762	1
values[47]	180	1			T74	15		T758	10		T762	1
values[48]	142	1			T74	3		T758	6		T762	1
values[49]	162	1			T74	10		T758	12		T762	1
values[50]	188	1			T74	11		T758	7		T762	1
values[51]	209	1			T74	6		T758	15		T762	1
values[52]	151	1			T74	6		T758	4		T762	1
values[53]	153	1			T74	10		T758	6		T762	1
values[54]	115	1			T74	11		T758	13		T762	1
values[55]	95	1			T74	11		T758	13		T762	1
values[56]	86	1			T74	20		T758	4		T762	1
values[57]	93	1			T74	24		T762	1		T770	2
values[58]	90	1			T74	21		T762	2		T770	3
values[59]	81	1			T74	15		T762	1		T770	2
values[60]	69	1			T74	19		T762	1		T770	2
values[61]	70	1			T74	14		T762	1		T770	2
values[62]	66	1			T74	8		T762	1		T770	2
values[63]	60	1			T74	7		T762	1		T770	2
values[64]	72	1			T74	10		T762	1		T770	2
values[65]	88	1			T74	8		T762	1		T770	2
values[66]	101	1			T74	14		T762	2		T770	2
values[67]	89	1			T74	12		T762	1		T770	2
values[68]	100	1			T74	8		T762	1		T770	2
values[69]	130	1			T74	11		T762	1		T770	2
values[70]	95	1			T74	8		T762	1		T770	2
values[71]	83	1			T74	9		T762	1		T770	2
values[72]	89	1			T74	8		T762	1		T770	2
values[73]	86	1			T74	11		T762	1		T770	2
values[74]	80	1			T74	8		T762	1		T770	2
values[75]	107	1			T74	12		T762	1		T770	2
values[76]	115	1			T74	11		T762	1		T770	3
values[77]	114	1			T74	11		T762	1		T770	3
values[78]	97	1			T74	9		T762	1		T770	5
values[79]	91	1			T74	10		T762	1		T770	4
values[80]	108	1			T74	7		T762	1		T770	4
values[81]	88	1			T74	5		T762	1		T770	5
values[82]	80	1			T74	9		T762	1		T770	2
values[83]	66	1			T74	7		T762	1		T770	5
values[84]	78	1			T74	7		T762	1		T770	13
values[85]	85	1			T74	9		T762	1		T770	10
values[86]	65	1			T74	2		T762	1		T770	3
values[87]	71	1			T74	11		T762	1		T770	4
values[88]	71	1			T74	6		T762	1		T770	4
values[89]	87	1			T74	12		T762	1		T770	4
values[90]	85	1			T74	11		T762	1		T770	5
values[91]	79	1			T74	12		T762	1		T770	3
values[92]	66	1			T74	14		T762	1		T770	2
values[93]	83	1			T74	9		T762	1		T770	2
values[94]	75	1			T74	5		T762	1		T770	3
values[95]	65	1			T74	9		T762	1		T770	2
values[96]	64	1			T74	6		T762	1		T770	4
values[97]	87	1			T74	3		T762	1		T770	12
values[98]	69	1			T74	4		T762	1		T770	7
values[99]	78	1			T74	3		T762	1		T770	7
values[100]	68	1			T74	5		T762	1		T770	3
values[101]	72	1			T74	12		T762	1		T770	7
values[102]	80	1			T74	8		T762	1		T770	4
values[103]	69	1			T74	4		T762	1		T770	6
values[104]	52	1			T74	4		T762	1		T770	3
values[105]	68	1			T74	9		T762	1		T770	9
values[106]	70	1			T74	2		T762	1		T770	2
values[107]	65	1			T74	2		T762	1		T770	3
values[108]	75	1			T74	2		T762	1		T770	4
values[109]	83	1			T74	3		T762	1		T770	7
values[110]	70	1			T74	1		T762	1		T770	4
values[111]	66	1			T74	1		T762	1		T770	5
values[112]	71	1			T762	1		T770	2		T787	2
values[113]	76	1			T762	1		T770	11		T787	5
values[114]	61	1			T762	1		T770	9		T787	1
values[115]	60	1			T762	1		T770	2		T787	2
values[116]	94	1			T762	1		T770	4		T787	2
values[117]	63	1			T762	1		T770	3		T787	1
values[118]	70	1			T762	1		T770	4		T787	5
values[119]	56	1			T762	1		T770	5		T787	1
values[120]	42	1			T762	1		T770	7		T787	1
values[121]	36	1			T762	1		T770	3		T787	1
values[122]	41	1			T762	1		T770	2		T787	2
values[123]	41	1			T762	6		T770	2		T787	3
values[124]	36	1			T762	5		T770	3		T787	2
values[125]	31	1			T762	1		T770	2		T787	2
values[126]	89	1			T762	8		T770	9		T787	2
values[127]	1142	1			T762	62		T770	108		T787	50
values[128]	5541	1			T762	277		T770	497		T787	272