Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	527	1			T74	1		T146	4		T514	2
all_values[1]	479	1			T146	2		T515	1		T514	2
all_values[2]	459	1			T74	1		T146	2		T514	2
all_values[3]	469	1			T237	1		T514	2		T788	2
all_values[4]	541	1			T69	1		T515	1		T514	2
all_values[5]	493	1			T146	4		T515	1		T514	2
all_values[6]	463	1			T74	2		T146	2		T514	2
all_values[7]	487	1			T69	1		T515	1		T788	1
all_values[8]	479	1			T146	4		T237	1		T514	1
all_values[9]	528	1			T146	5		T515	1		T426	1
all_values[10]	491	1			T69	2		T146	2		T514	1
all_values[11]	486	1			T146	4		T515	1		T514	1
all_values[12]	491	1			T74	1		T146	4		T788	1
all_values[13]	487	1			T146	4		T514	5		T619	5
all_values[14]	514	1			T69	1		T74	1		T146	5
all_values[15]	468	1			T74	1		T146	4		T788	1
all_values[16]	474	1			T69	1		T146	3		T515	1
all_values[17]	488	1			T74	1		T146	3		T426	1
all_values[18]	458	1			T69	1		T146	2		T515	1
all_values[19]	525	1			T146	4		T514	4		T788	2
all_values[20]	511	1			T69	1		T146	6		T623	1
all_values[21]	476	1			T146	3		T515	2		T514	1
all_values[22]	512	1			T146	4		T514	2		T788	1
all_values[23]	486	1			T74	1		T146	1		T514	2
all_values[24]	508	1			T146	2		T515	1		T514	3
all_values[25]	494	1			T146	7		T515	1		T426	1
all_values[26]	465	1			T146	3		T623	1		T788	1
all_values[27]	518	1			T146	7		T515	1		T788	1
all_values[28]	486	1			T146	2		T514	2		T619	7
all_values[29]	517	1			T146	1		T515	1		T788	2
all_values[30]	501	1			T146	7		T623	1		T514	2
all_values[31]	489	1			T146	2		T619	4		T756	1
all_values[32]	519	1			T74	1		T146	3		T514	2
all_values[33]	489	1			T74	1		T146	4		T514	5
all_values[34]	476	1			T146	2		T623	1		T514	6
all_values[35]	457	1			T146	5		T619	3		T405	1
all_values[36]	524	1			T69	1		T146	7		T426	1
all_values[37]	492	1			T74	1		T146	4		T514	2
all_values[38]	465	1			T146	2		T514	3		T541	2
all_values[39]	476	1			T146	1		T514	2		T619	3
all_values[40]	513	1			T146	1		T619	5		T554	8
all_values[41]	512	1			T146	4		T514	3		T788	3
all_values[42]	522	1			T74	1		T146	3		T619	3
all_values[43]	524	1			T69	1		T146	2		T515	1
all_values[44]	499	1			T146	7		T623	2		T514	2
all_values[45]	492	1			T69	1		T146	3		T237	1
all_values[46]	517	1			T69	1		T74	1		T146	4
all_values[47]	501	1			T146	6		T514	3		T619	1
all_values[48]	512	1			T69	1		T74	2		T146	4
all_values[49]	474	1			T74	1		T146	6		T788	1