Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3684	1			T146	13		T237	1		T512	3
all_values[1]	3667	1			T146	8		T237	5		T512	4
all_values[2]	3595	1			T146	12		T237	1		T512	2
all_values[3]	3703	1			T146	20		T237	9		T512	5
all_values[4]	3623	1			T146	16		T237	2		T512	1
all_values[5]	3483	1			T146	16		T237	1		T512	4
all_values[6]	3586	1			T146	22		T237	1		T512	4
all_values[7]	3605	1			T146	27		T237	4		T512	5
all_values[8]	3585	1			T146	25		T237	3		T512	2
all_values[9]	3635	1			T146	27		T237	1		T512	1
all_values[10]	3622	1			T146	10		T237	3		T512	1
all_values[11]	3627	1			T146	21		T237	2		T512	6
all_values[12]	3766	1			T146	22		T512	5		T514	8
all_values[13]	3633	1			T146	21		T237	6		T512	1
all_values[14]	3591	1			T146	14		T237	1		T512	4
all_values[15]	3652	1			T146	16		T237	1		T512	3
all_values[16]	3582	1			T146	17		T512	2		T426	1
all_values[17]	3669	1			T146	20		T237	1		T512	2
all_values[18]	3635	1			T146	17		T237	3		T512	9
all_values[19]	3626	1			T146	27		T237	2		T512	4
all_values[20]	3587	1			T146	18		T237	1		T512	2
all_values[21]	3662	1			T146	10		T237	2		T512	1
all_values[22]	3694	1			T146	16		T237	1		T512	4
all_values[23]	3593	1			T146	18		T237	5		T512	3
all_values[24]	3613	1			T146	18		T237	3		T512	1
all_values[25]	3660	1			T146	28		T512	7		T514	5
all_values[26]	3606	1			T146	17		T237	3		T512	7
all_values[27]	3587	1			T146	17		T237	3		T512	2
all_values[28]	3624	1			T146	19		T237	2		T512	2
all_values[29]	3575	1			T146	13		T512	2		T426	1
all_values[30]	3551	1			T146	22		T512	1		T426	1
all_values[31]	3563	1			T146	12		T237	5		T512	1
all_values[32]	3730	1			T146	19		T237	2		T512	4
all_values[33]	3588	1			T146	18		T237	4		T512	2
all_values[34]	3591	1			T146	13		T237	2		T512	3
all_values[35]	3683	1			T146	22		T237	3		T512	7
all_values[36]	3622	1			T146	19		T237	3		T512	2
all_values[37]	3590	1			T146	22		T237	2		T512	5
all_values[38]	3624	1			T146	11		T237	5		T512	2
all_values[39]	3645	1			T146	18		T237	2		T512	2
all_values[40]	3494	1			T146	15		T237	2		T512	1
all_values[41]	3601	1			T146	19		T237	1		T512	5
all_values[42]	3672	1			T146	24		T237	4		T512	1
all_values[43]	3662	1			T146	13		T237	3		T512	4
all_values[44]	3576	1			T146	19		T237	3		T512	1
all_values[45]	3631	1			T146	18		T237	4		T426	2
all_values[46]	3700	1			T146	12		T237	4		T512	3
all_values[47]	3610	1			T146	11		T237	2		T512	2
all_values[48]	3607	1			T146	12		T237	3		T512	2
all_values[49]	3701	1			T146	23		T237	5		T512	4
all_values[50]	3745	1			T146	25		T512	3		T426	2
all_values[51]	3653	1			T146	26		T237	3		T512	4
all_values[52]	3648	1			T146	14		T237	3		T512	6
all_values[53]	3642	1			T146	15		T237	1		T512	2
all_values[54]	3591	1			T146	19		T237	2		T512	1
all_values[55]	3576	1			T146	14		T237	2		T512	3
all_values[56]	3560	1			T146	19		T237	3		T512	5
all_values[57]	3694	1			T146	21		T237	3		T512	6
all_values[58]	3603	1			T146	18		T512	6		T426	1
all_values[59]	3593	1			T146	16		T237	2		T512	3
all_values[60]	3753	1			T146	17		T237	1		T512	3
all_values[61]	3616	1			T146	17		T237	3		T512	1
all_values[62]	3610	1			T146	19		T237	5		T512	1
all_values[63]	3702	1			T146	11		T237	2		T426	1