Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3619742	1			T73	135		T75	85		T78	1773
values[2]	745369	1			T73	45		T75	36		T78	536
values[3]	109541	1			T73	1		T78	36		T118	111
values[4]	59672	1			T118	3		T227	1		T508	5
values[5]	39663	1			T710	141		T423	7		T417	52
values[6]	29266	1			T710	74		T423	7		T417	50
values[7]	23548	1			T710	60		T423	4		T417	49
values[8]	19985	1			T710	51		T423	16		T417	43
values[9]	17645	1			T710	52		T423	13		T417	55
values[10]	16238	1			T710	32		T423	19		T417	74
values[11]	15044	1			T710	39		T423	9		T417	32
values[12]	14172	1			T710	49		T423	9		T417	30
values[13]	13599	1			T710	35		T423	14		T417	44
values[14]	12937	1			T710	34		T423	16		T417	47
values[15]	12399	1			T710	22		T423	9		T417	38
values[16]	11620	1			T710	11		T423	5		T417	34
values[17]	11056	1			T710	10		T423	6		T417	43
values[18]	10426	1			T710	11		T423	4		T417	29
values[19]	10050	1			T710	6		T423	3		T417	35
values[20]	10028	1			T710	4		T423	13		T417	43
values[21]	9710	1			T710	5		T423	21		T417	49
values[22]	9421	1			T710	11		T423	17		T417	46
values[23]	9027	1			T710	6		T423	7		T417	37
values[24]	8448	1			T710	7		T423	6		T417	22
values[25]	8309	1			T710	4		T423	3		T417	16
values[26]	8066	1			T710	4		T423	9		T417	18
values[27]	7554	1			T710	4		T423	5		T417	26
values[28]	7284	1			T710	4		T423	12		T417	22
values[29]	7103	1			T710	8		T423	8		T417	50
values[30]	6481	1			T710	8		T423	2		T417	47
values[31]	6032	1			T710	3		T423	3		T417	38
values[32]	5523	1			T710	6		T423	4		T417	41
values[33]	5134	1			T710	5		T423	4		T417	37
values[34]	4981	1			T710	7		T423	3		T417	18
values[35]	4737	1			T710	5		T423	4		T417	14
values[36]	4509	1			T710	8		T423	4		T417	7
values[37]	4255	1			T710	5		T423	6		T417	6
values[38]	3966	1			T710	8		T423	7		T417	8
values[39]	3807	1			T710	6		T423	5		T417	7
values[40]	3714	1			T710	8		T423	4		T417	3
values[41]	3646	1			T710	3		T423	5		T417	5
values[42]	3555	1			T710	4		T423	6		T417	5
values[43]	3547	1			T710	4		T423	4		T417	7
values[44]	3543	1			T710	3		T423	3		T417	4
values[45]	3334	1			T710	7		T423	4		T417	8
values[46]	3270	1			T710	4		T423	4		T417	9
values[47]	3207	1			T710	4		T423	3		T417	3
values[48]	3188	1			T710	4		T423	4		T417	7
values[49]	3043	1			T710	4		T423	3		T417	1
values[50]	3046	1			T710	5		T423	2		T417	1
values[51]	2977	1			T710	6		T423	2		T417	3
values[52]	2841	1			T710	13		T423	2		T417	1
values[53]	2768	1			T710	5		T423	2		T507	7
values[54]	2753	1			T710	5		T423	1		T507	3
values[55]	2702	1			T710	5		T423	1		T507	3
values[56]	2701	1			T710	7		T423	2		T507	3
values[57]	2550	1			T710	6		T423	2		T507	5
values[58]	2568	1			T710	6		T423	2		T507	3
values[59]	2609	1			T710	7		T423	2		T507	5
values[60]	2614	1			T710	11		T423	2		T507	4
values[61]	2866	1			T710	12		T423	2		T507	3
values[62]	4344	1			T710	32		T423	2		T507	3
values[63]	11762	1			T710	118		T423	3		T507	7
values[64]	241954	1			T710	258		T423	57		T507	121

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4682102	1			T73	144		T75	105		T78	1985
values[2]	810514	1			T73	34		T75	28		T78	491
values[3]	88462	1			T73	7		T75	1		T78	78
values[4]	15613	1			T73	1		T78	3		T118	27
values[5]	5946	1			T118	9		T508	11		T710	3
values[6]	3800	1			T118	4		T508	5		T710	5
values[7]	2896	1			T118	2		T508	1		T710	6
values[8]	2406	1			T710	5		T423	2		T416	2
values[9]	2262	1			T710	4		T423	2		T416	2
values[10]	1994	1			T710	10		T423	2		T416	2
values[11]	1749	1			T710	6		T423	2		T416	2
values[12]	1507	1			T710	12		T423	2		T416	2
values[13]	1344	1			T710	9		T423	1		T416	2
values[14]	1247	1			T710	5		T423	2		T416	2
values[15]	1197	1			T710	10		T423	2		T416	2
values[16]	1194	1			T710	3		T423	2		T416	2
values[17]	1110	1			T710	3		T423	2		T416	2
values[18]	1044	1			T710	3		T423	2		T416	2
values[19]	1098	1			T710	4		T423	2		T416	2
values[20]	968	1			T710	7		T423	2		T416	3
values[21]	895	1			T710	7		T423	2		T416	2
values[22]	941	1			T710	4		T423	2		T416	2
values[23]	905	1			T710	7		T423	2		T416	2
values[24]	864	1			T710	6		T423	3		T416	2
values[25]	835	1			T710	11		T423	2		T416	2
values[26]	789	1			T710	9		T423	2		T416	2
values[27]	813	1			T710	6		T423	2		T416	2
values[28]	807	1			T710	4		T423	2		T416	2
values[29]	763	1			T710	8		T423	2		T416	2
values[30]	752	1			T710	3		T423	2		T416	2
values[31]	648	1			T710	3		T423	1		T416	2
values[32]	703	1			T710	3		T423	1		T416	2
values[33]	727	1			T710	8		T423	2		T416	2
values[34]	695	1			T710	6		T423	2		T416	2
values[35]	716	1			T710	4		T423	2		T416	2
values[36]	622	1			T710	4		T423	2		T416	2
values[37]	616	1			T710	7		T423	2		T416	2
values[38]	524	1			T710	6		T423	2		T416	2
values[39]	514	1			T710	4		T423	2		T416	2
values[40]	545	1			T710	4		T423	2		T416	2
values[41]	561	1			T710	7		T423	2		T416	2
values[42]	524	1			T710	8		T423	2		T416	1
values[43]	518	1			T710	4		T423	3		T416	1
values[44]	514	1			T710	8		T423	2		T416	2
values[45]	512	1			T710	8		T423	2		T416	2
values[46]	521	1			T710	7		T423	2		T416	2
values[47]	497	1			T710	3		T423	2		T416	2
values[48]	461	1			T710	3		T423	2		T416	2
values[49]	483	1			T710	3		T423	2		T416	2
values[50]	464	1			T710	4		T423	2		T416	2
values[51]	513	1			T710	7		T423	2		T416	2
values[52]	505	1			T710	16		T423	2		T416	2
values[53]	433	1			T710	6		T423	2		T416	3
values[54]	447	1			T710	4		T423	2		T416	2
values[55]	457	1			T710	6		T423	2		T416	2
values[56]	464	1			T710	6		T423	2		T416	2
values[57]	436	1			T710	6		T423	2		T416	2
values[58]	405	1			T710	4		T423	2		T416	2
values[59]	407	1			T710	7		T423	2		T416	2
values[60]	430	1			T710	4		T423	1		T416	2
values[61]	465	1			T710	8		T423	1		T416	3
values[62]	723	1			T710	27		T423	2		T416	2
values[63]	2890	1			T710	131		T423	6		T416	3
values[64]	26614	1			T710	348		T423	110		T416	159

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	546007	1			T73	1		T75	1		T78	29
values[2]	2562113	1			T73	98		T75	120		T78	1418
values[3]	1190874	1			T73	80		T75	76		T78	1005
values[4]	149332	1			T73	3		T78	29		T118	20
values[5]	79972	1			T118	3		T227	2		T508	2
values[6]	52248	1			T710	172		T423	15		T417	81
values[7]	38405	1			T710	66		T423	13		T417	49
values[8]	30339	1			T710	43		T423	8		T417	54
values[9]	25271	1			T710	21		T423	2		T417	67
values[10]	22497	1			T710	12		T423	4		T417	54
values[11]	19852	1			T710	10		T423	1		T417	52
values[12]	18277	1			T710	10		T423	5		T417	43
values[13]	16798	1			T710	27		T423	21		T417	57
values[14]	15596	1			T710	47		T423	8		T417	61
values[15]	14970	1			T710	71		T423	5		T417	51
values[16]	14230	1			T710	68		T423	2		T417	61
values[17]	13555	1			T710	42		T423	9		T417	49
values[18]	12830	1			T710	30		T423	3		T417	52
values[19]	12359	1			T710	12		T423	8		T417	66
values[20]	11963	1			T710	11		T423	26		T417	67
values[21]	11134	1			T710	12		T423	11		T417	82
values[22]	10700	1			T710	6		T423	2		T417	57
values[23]	10287	1			T710	7		T423	8		T417	40
values[24]	9866	1			T710	5		T423	11		T417	29
values[25]	9475	1			T710	5		T423	7		T417	15
values[26]	9118	1			T710	9		T423	11		T417	10
values[27]	9062	1			T710	5		T423	9		T417	11
values[28]	8202	1			T710	3		T423	2		T417	19
values[29]	7699	1			T710	5		T423	2		T417	20
values[30]	7366	1			T710	6		T423	4		T417	19
values[31]	6919	1			T710	3		T423	2		T417	10
values[32]	6278	1			T710	3		T423	2		T417	15
values[33]	5925	1			T710	9		T423	3		T417	12
values[34]	5419	1			T710	4		T417	5		T507	4
values[35]	5260	1			T710	4		T417	14		T507	16
values[36]	4857	1			T710	9		T417	20		T507	14
values[37]	4644	1			T710	11		T417	24		T507	14
values[38]	4471	1			T710	5		T417	14		T507	6
values[39]	4211	1			T710	6		T417	11		T507	9
values[40]	4010	1			T710	6		T417	11		T507	1
values[41]	4005	1			T710	12		T417	2		T507	4
values[42]	3904	1			T710	6		T417	1		T507	1
values[43]	3799	1			T710	5		T417	3		T507	2
values[44]	3676	1			T710	8		T417	2		T507	1
values[45]	3644	1			T710	7		T417	1		T507	1
values[46]	3604	1			T710	8		T417	3		T507	2
values[47]	3477	1			T710	7		T417	1		T507	1
values[48]	3380	1			T710	7		T417	1		T507	3
values[49]	3461	1			T710	4		T417	3		T507	1
values[50]	3240	1			T710	3		T417	2		T507	2
values[51]	3192	1			T710	3		T417	2		T507	1
values[52]	3199	1			T710	3		T417	1		T507	1
values[53]	3151	1			T710	4		T417	2		T507	2
values[54]	3133	1			T710	9		T417	1		T507	1
values[55]	3004	1			T710	5		T507	1		T452	3
values[56]	2883	1			T710	4		T507	1		T452	1
values[57]	2819	1			T710	5		T507	1		T452	2
values[58]	2932	1			T710	5		T507	1		T452	3
values[59]	2921	1			T710	4		T507	1		T452	4
values[60]	2820	1			T710	4		T507	1		T452	3
values[61]	3010	1			T710	8		T507	3		T452	2
values[62]	4027	1			T710	16		T507	2		T452	14
values[63]	9914	1			T710	89		T507	2		T452	33
values[64]	233907	1			T710	390		T507	112		T452	42