Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2419304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32522256

1

T4

16535

T1

6910

T5

4887

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23787224	1			T4	12639		T1	3199		T5	1702
values[0x0]	9444182	1			T4	3896		T1	3711		T5	3185
values[0x1]	1710154	1			T4	3630		T1	447		T5	204

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	782717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34158843

1

T4

20165

T1

7357

T5

5091

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16115084	1			T4	10083		T1	3679		T5	2546
valid_sources[0x01]	16113376	1			T4	10082		T1	3678		T5	2545
valid_sources[0x02]	44377	1			T65	1		T2	1		T74	213
valid_sources[0x03]	44308	1			T79	4		T74	142		T138	146
valid_sources[0x04]	43235	1			T2	2		T74	115		T138	118
valid_sources[0x05]	42821	1			T2	1		T74	152		T138	188
valid_sources[0x06]	43404	1			T194	1		T74	105		T138	125
valid_sources[0x07]	43193	1			T194	1		T74	125		T138	149
valid_sources[0x08]	43636	1			T2	1		T74	218		T138	257
valid_sources[0x09]	44500	1			T74	159		T138	202		T139	396
valid_sources[0x0a]	47382	1			T194	1		T74	97		T138	119
valid_sources[0x0b]	44533	1			T74	176		T138	151		T139	397
valid_sources[0x0c]	43926	1			T74	226		T138	106		T139	368
valid_sources[0x0d]	43837	1			T74	156		T138	193		T139	435
valid_sources[0x0e]	42592	1			T65	1		T2	1		T194	1
valid_sources[0x0f]	43817	1			T2	2		T194	1		T79	11
valid_sources[0x10]	43237	1			T194	1		T74	180		T138	146
valid_sources[0x11]	43669	1			T74	204		T138	170		T139	402
valid_sources[0x12]	43721	1			T65	6		T74	153		T138	142
valid_sources[0x13]	44173	1			T65	2		T194	1		T74	144
valid_sources[0x14]	43307	1			T79	3		T74	217		T138	199
valid_sources[0x15]	45437	1			T2	2		T194	1		T74	212
valid_sources[0x16]	43722	1			T74	187		T138	215		T139	405
valid_sources[0x17]	47262	1			T65	2		T74	156		T138	159
valid_sources[0x18]	42804	1			T74	143		T138	171		T139	391
valid_sources[0x19]	41656	1			T2	1		T74	168		T138	146
valid_sources[0x1a]	42974	1			T65	1		T194	1		T195	39
valid_sources[0x1b]	43466	1			T65	2		T2	1		T74	172
valid_sources[0x1c]	43405	1			T65	1		T2	1		T194	1
valid_sources[0x1d]	43356	1			T2	3		T74	171		T138	150
valid_sources[0x1e]	43236	1			T65	1		T74	145		T138	167
valid_sources[0x1f]	46313	1			T194	1		T74	144		T138	140
valid_sources[0x20]	43439	1			T2	1		T74	239		T138	186

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22882552

1

T4

12639

T1

3199

T5

1702

values[0x0]

all_enables

biggest_size

9397375

1

T4

3896

T1

3711

T5

3185

values[0x1]

all_enables

biggest_size

242329

1

T65

20

T2

17

T77

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2856484	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

451938

1

T73

24

T75

23

T78

311

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1119425	1			T73	53		T75	39		T78	782
values[0x0]	1069273	1			T73	62		T75	43		T78	770
values[0x1]	1119724	1			T73	66		T75	39		T78	793

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2212459	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1095963

1

T73

51

T75

48

T78

818

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50879	1			T78	29		T118	5		T225	1
valid_sources[0x01]	51930	1			T78	36		T118	22		T393	47
valid_sources[0x02]	51684	1			T78	36		T118	21		T225	1
valid_sources[0x03]	50800	1			T73	6		T75	6		T78	39
valid_sources[0x04]	51239	1			T78	34		T118	13		T225	1
valid_sources[0x05]	52128	1			T78	40		T118	24		T393	34
valid_sources[0x06]	51654	1			T78	26		T118	22		T393	30
valid_sources[0x07]	50587	1			T75	9		T78	44		T118	1
valid_sources[0x08]	50817	1			T73	4		T78	49		T118	21
valid_sources[0x09]	50270	1			T78	31		T118	43		T278	8
valid_sources[0x0a]	52061	1			T73	4		T75	1		T78	30
valid_sources[0x0b]	51979	1			T73	34		T75	4		T78	48
valid_sources[0x0c]	51886	1			T78	22		T118	6		T393	24
valid_sources[0x0d]	51184	1			T78	41		T118	17		T393	40
valid_sources[0x0e]	52487	1			T78	34		T118	24		T278	14
valid_sources[0x0f]	52367	1			T78	39		T118	4		T393	25
valid_sources[0x10]	51189	1			T78	35		T118	15		T278	19
valid_sources[0x11]	51693	1			T78	34		T118	4		T393	38
valid_sources[0x12]	51513	1			T73	7		T78	27		T118	39
valid_sources[0x13]	51017	1			T73	7		T75	1		T78	33
valid_sources[0x14]	50021	1			T78	43		T118	17		T393	63
valid_sources[0x15]	52126	1			T78	23		T118	15		T225	4
valid_sources[0x16]	52138	1			T73	5		T75	4		T78	48
valid_sources[0x17]	52000	1			T73	10		T75	1		T78	43
valid_sources[0x18]	50757	1			T73	2		T75	1		T78	51
valid_sources[0x19]	51263	1			T78	36		T118	15		T393	32
valid_sources[0x1a]	51311	1			T73	5		T78	30		T118	16
valid_sources[0x1b]	52282	1			T78	41		T118	33		T278	10
valid_sources[0x1c]	53106	1			T73	1		T78	43		T118	22
valid_sources[0x1d]	50819	1			T78	32		T118	5		T393	25
valid_sources[0x1e]	51039	1			T73	1		T78	44		T118	21
valid_sources[0x1f]	51739	1			T78	50		T118	8		T278	2
valid_sources[0x20]	50659	1			T73	13		T78	37		T118	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47300

1

T73

1

T75

3

T78

26

values[0x0]

all_enables

biggest_size

357356

1

T73

23

T75

16

T78

250

values[0x1]

all_enables

biggest_size

47282

1

T75

4

T78

35

T118

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3054517	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

498438

1

T73

26

T75

18

T78

345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1216209	1			T73	68		T75	38		T78	865
values[0x0]	1121693	1			T73	59		T75	45		T78	831
values[0x1]	1215053	1			T73	59		T75	51		T78	861

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2344886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1208069

1

T73

76

T75

48

T78

860

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55355	1			T78	66		T118	13		T278	2
valid_sources[0x01]	55643	1			T73	3		T78	33		T118	14
valid_sources[0x02]	55203	1			T73	5		T78	24		T118	24
valid_sources[0x03]	54683	1			T73	2		T78	35		T118	11
valid_sources[0x04]	55606	1			T73	5		T78	37		T118	15
valid_sources[0x05]	55781	1			T78	42		T118	27		T225	2
valid_sources[0x06]	55979	1			T73	3		T75	2		T78	28
valid_sources[0x07]	55091	1			T73	4		T78	47		T118	12
valid_sources[0x08]	55593	1			T73	4		T75	2		T78	31
valid_sources[0x09]	54898	1			T73	8		T75	5		T78	30
valid_sources[0x0a]	54268	1			T73	4		T75	27		T78	38
valid_sources[0x0b]	55705	1			T73	2		T75	2		T78	29
valid_sources[0x0c]	54707	1			T75	5		T78	65		T118	12
valid_sources[0x0d]	56018	1			T73	5		T78	77		T118	18
valid_sources[0x0e]	55915	1			T73	2		T78	45		T118	29
valid_sources[0x0f]	55128	1			T73	5		T78	20		T118	16
valid_sources[0x10]	56009	1			T73	5		T75	3		T78	42
valid_sources[0x11]	55760	1			T73	6		T78	10		T118	20
valid_sources[0x12]	55608	1			T73	2		T78	48		T118	22
valid_sources[0x13]	55903	1			T73	1		T78	48		T118	19
valid_sources[0x14]	55678	1			T73	11		T78	36		T118	35
valid_sources[0x15]	55622	1			T73	10		T78	32		T118	32
valid_sources[0x16]	55601	1			T73	4		T78	53		T118	22
valid_sources[0x17]	55577	1			T73	1		T75	2		T78	45
valid_sources[0x18]	54690	1			T73	5		T75	1		T78	61
valid_sources[0x19]	55413	1			T73	2		T78	56		T118	17
valid_sources[0x1a]	55317	1			T73	1		T78	32		T118	32
valid_sources[0x1b]	55606	1			T78	61		T118	19		T393	56
valid_sources[0x1c]	56041	1			T75	3		T78	8		T118	36
valid_sources[0x1d]	55031	1			T78	39		T118	22		T278	2
valid_sources[0x1e]	53777	1			T78	23		T118	16		T278	3
valid_sources[0x1f]	55896	1			T73	1		T78	14		T118	19
valid_sources[0x20]	55455	1			T73	5		T78	19		T118	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51771

1

T73

5

T75

2

T78

28

values[0x0]

all_enables

biggest_size

394498

1

T73

20

T75

16

T78

280

values[0x1]

all_enables

biggest_size

52169

1

T73

1

T78

37

T118

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2887688	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455913

1

T73

23

T75

22

T78

327

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130989	1			T73	52		T75	56		T78	858
values[0x0]	1080352	1			T73	64		T75	63		T78	818
values[0x1]	1132260	1			T73	66		T75	78		T78	805

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2236958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1106643

1

T73

52

T75

61

T78

798

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51551	1			T73	2		T75	10		T78	29
valid_sources[0x01]	52646	1			T73	3		T78	56		T118	19
valid_sources[0x02]	52538	1			T73	5		T75	6		T78	40
valid_sources[0x03]	52894	1			T73	3		T78	31		T118	27
valid_sources[0x04]	51199	1			T73	5		T75	2		T78	58
valid_sources[0x05]	52648	1			T73	2		T78	42		T118	29
valid_sources[0x06]	52256	1			T73	2		T78	52		T118	19
valid_sources[0x07]	51992	1			T73	2		T75	12		T78	21
valid_sources[0x08]	52631	1			T75	5		T78	36		T118	24
valid_sources[0x09]	52465	1			T73	1		T75	1		T78	39
valid_sources[0x0a]	51627	1			T73	2		T75	5		T78	42
valid_sources[0x0b]	52242	1			T73	3		T78	31		T118	13
valid_sources[0x0c]	51814	1			T78	45		T118	15		T393	47
valid_sources[0x0d]	51923	1			T73	5		T78	27		T118	21
valid_sources[0x0e]	52465	1			T73	7		T78	17		T118	12
valid_sources[0x0f]	52672	1			T78	34		T118	14		T278	2
valid_sources[0x10]	52678	1			T73	2		T75	1		T78	35
valid_sources[0x11]	52709	1			T73	4		T75	6		T78	70
valid_sources[0x12]	52371	1			T73	2		T75	5		T78	34
valid_sources[0x13]	52443	1			T73	5		T78	43		T118	23
valid_sources[0x14]	51978	1			T73	1		T78	22		T118	30
valid_sources[0x15]	52249	1			T73	2		T78	32		T118	23
valid_sources[0x16]	52483	1			T73	9		T75	12		T78	39
valid_sources[0x17]	52404	1			T73	4		T78	22		T118	17
valid_sources[0x18]	52625	1			T73	7		T75	7		T78	41
valid_sources[0x19]	51894	1			T73	5		T78	42		T118	21
valid_sources[0x1a]	52504	1			T73	1		T78	38		T118	29
valid_sources[0x1b]	51892	1			T73	5		T75	5		T78	60
valid_sources[0x1c]	53621	1			T73	7		T75	5		T78	37
valid_sources[0x1d]	52228	1			T73	4		T75	12		T78	52
valid_sources[0x1e]	50868	1			T73	3		T78	42		T118	11
valid_sources[0x1f]	52813	1			T73	1		T75	1		T78	45
valid_sources[0x20]	51732	1			T75	7		T78	25		T118	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47406

1

T75

2

T78

40

T118

18

values[0x0]

all_enables

biggest_size

360520

1

T73

20

T75

20

T78

259

values[0x1]

all_enables

biggest_size

47987

1

T73

3

T78

28

T118

16