Unified Coverage Report :: Module :: gpio

Module : gpio

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_gpio	100.00			100.00

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Module Instance : tb.dut.top_earlgrey.u_gpio

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : gpio

	Total	Covered	Percent
Totals	33	33	100.00
Total Bits	540	540	100.00
Total Bits 0->1	270	270	100.00
Total Bits 1->0	270	270	100.00

Ports	33	33	100.00
Port Bits	540	540	100.00
Port Bits 0->1	270	270	100.00
Port Bits 1->0	270	270	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_i.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	INPUT
tl_i.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_o.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_o.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T232,T308,T32	Yes	T232,T308,T32	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T232,T308,T32	Yes	T1,T232,T104	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T232,T308,T32	Yes	T1,T232,T104	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T78,T118	Yes	T73,T75,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T118	Yes	T77,T73,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T15,*T59	Yes	T4,T1,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
intr_gpio_o[31:0]	Yes	Yes	T232,T308,T32	Yes	T232,T308,T32	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T83,T77	Yes	T82,T83,T77	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T83,T77	Yes	T82,T83,T77	OUTPUT
cio_gpio_i[31:0]	Yes	Yes	T32,T33,T84	Yes	T32,T33,T84	INPUT
cio_gpio_o[31:0]	Yes	Yes	T1,T32,T33	Yes	T1,T32,T33	OUTPUT
cio_gpio_en_o[31:0]	Yes	Yes	T32,T33,T77	Yes	T1,T32,T33	OUTPUT

*Tests covering at least one bit in the range