Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470344557	52642362	0	0
DepthKnown_A	470344557	470241299	0	0
RvalidKnown_A	470344557	470241299	0	0
WreadyKnown_A	470344557	470241299	0	0
gen_passthru_fifo.paramCheckPass	980	980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	52642362	0	0
T1	110167	13894	0	0
T4	214119	21461	0	0
T5	69071	8187	0	0
T15	136331	156636	0	0
T38	233928	30679	0	0
T59	177554	21449	0	0
T86	74681	8692	0	0
T87	126119	172450	0	0
T88	145625	19724	0	0
T89	216296	29162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470344557	40536841	0	0
DepthKnown_A	470344557	470241299	0	0
RvalidKnown_A	470344557	470241299	0	0
WreadyKnown_A	470344557	470241299	0	0
gen_passthru_fifo.paramCheckPass	980	980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	40536841	0	0
T1	110167	10437	0	0
T4	214119	17583	0	0
T5	69071	5455	0	0
T15	136331	110166	0	0
T38	233928	21140	0	0
T59	177554	16288	0	0
T86	74681	5891	0	0
T87	126119	151894	0	0
T88	145625	14596	0	0
T89	216296	25417	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470344557	35985664	0	0
DepthKnown_A	470344557	470241299	0	0
RvalidKnown_A	470344557	470241299	0	0
WreadyKnown_A	470344557	470241299	0	0
gen_passthru_fifo.paramCheckPass	980	980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	35985664	0	0
T1	110167	7596	0	0
T4	214119	20369	0	0
T5	69071	5676	0	0
T15	136331	75226	0	0
T38	233928	14990	0	0
T59	177554	11395	0	0
T86	74681	4228	0	0
T87	126119	287188	0	0
T88	145625	8512	0	0
T89	216296	6877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470344557	32232808	0	0
DepthKnown_A	470344557	470241299	0	0
RvalidKnown_A	470344557	470241299	0	0
WreadyKnown_A	470344557	470241299	0	0
gen_passthru_fifo.paramCheckPass	980	980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	32232808	0	0
T1	110167	7357	0	0
T4	214119	20165	0	0
T5	69071	5091	0	0
T15	136331	73050	0	0
T38	233928	14615	0	0
T59	177554	11095	0	0
T86	74681	4037	0	0
T87	126119	286738	0	0
T88	145625	8234	0	0
T89	216296	6638	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	470241299	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555590086	101287	0	0
DepthKnown_A	555590086	555474907	0	0
RvalidKnown_A	555590086	555474907	0	0
WreadyKnown_A	555590086	555474907	0	0
gen_passthru_fifo.paramCheckPass	2871	2871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	101287	0	0
T1	110167	29	0	0
T4	214119	53	0	0
T5	69071	34	0	0
T15	136331	288	0	0
T38	233928	151	0	0
T59	177554	30	0	0
T86	74681	27	0	0
T87	126119	89	0	0
T88	145625	26	0	0
T89	216296	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2871	2871	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555590086	103683	0	0
DepthKnown_A	555590086	555474907	0	0
RvalidKnown_A	555590086	555474907	0	0
WreadyKnown_A	555590086	555474907	0	0
gen_passthru_fifo.paramCheckPass	2871	2871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	103683	0	0
T1	110167	29	0	0
T4	214119	53	0	0
T5	69071	34	0	0
T15	136331	288	0	0
T38	233928	151	0	0
T59	177554	30	0	0
T86	74681	27	0	0
T87	126119	89	0	0
T88	145625	26	0	0
T89	216296	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2871	2871	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555590086	52711	0	0
DepthKnown_A	555590086	555474907	0	0
RvalidKnown_A	555590086	555474907	0	0
WreadyKnown_A	555590086	555474907	0	0
gen_passthru_fifo.paramCheckPass	2871	2871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	52711	0	0
T1	110167	26	0	0
T4	214119	52	0	0
T5	69071	33	0	0
T15	136331	252	0	0
T38	233928	95	0	0
T59	177554	24	0	0
T86	74681	24	0	0
T87	126119	40	0	0
T88	145625	23	0	0
T89	216296	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2871	2871	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555590086	52710	0	0
DepthKnown_A	555590086	555474907	0	0
RvalidKnown_A	555590086	555474907	0	0
WreadyKnown_A	555590086	555474907	0	0
gen_passthru_fifo.paramCheckPass	2871	2871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	52710	0	0
T1	110167	26	0	0
T4	214119	52	0	0
T5	69071	33	0	0
T15	136331	252	0	0
T38	233928	95	0	0
T59	177554	24	0	0
T86	74681	24	0	0
T87	126119	40	0	0
T88	145625	23	0	0
T89	216296	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2871	2871	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555590086	48576	0	0
DepthKnown_A	555590086	555474907	0	0
RvalidKnown_A	555590086	555474907	0	0
WreadyKnown_A	555590086	555474907	0	0
gen_passthru_fifo.paramCheckPass	2871	2871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	48576	0	0
T1	110167	3	0	0
T4	214119	1	0	0
T5	69071	1	0	0
T15	136331	36	0	0
T38	233928	56	0	0
T59	177554	6	0	0
T86	74681	3	0	0
T87	126119	49	0	0
T88	145625	3	0	0
T89	216296	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2871	2871	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555590086	50973	0	0
DepthKnown_A	555590086	555474907	0	0
RvalidKnown_A	555590086	555474907	0	0
WreadyKnown_A	555590086	555474907	0	0
gen_passthru_fifo.paramCheckPass	2871	2871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	50973	0	0
T1	110167	3	0	0
T4	214119	1	0	0
T5	69071	1	0	0
T15	136331	36	0	0
T38	233928	56	0	0
T59	177554	6	0	0
T86	74681	3	0	0
T87	126119	49	0	0
T88	145625	3	0	0
T89	216296	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555590086	555474907	0	0
T1	110167	110112	0	0
T4	214119	214061	0	0
T5	69071	69020	0	0
T15	136331	136258	0	0
T38	233928	233826	0	0
T59	177554	177445	0	0
T86	74681	74630	0	0
T87	126119	126113	0	0
T88	145625	145563	0	0
T89	216296	216234	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2871	2871	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T38	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0