Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
rst_ni Yes Yes T15,T59,T38 Yes T4,T1,T5 INPUT
tl_i.d_ready Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T366,T53 Yes T4,T366,T53 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T366,T53 Yes T4,T366,T53 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[5:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T65,*T2,*T76 Yes T65,T2,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T65,T2,T77 Yes T65,T2,T77 INPUT
tl_i.a_valid Yes Yes T4,T366,T53 Yes T4,T366,T53 INPUT
tl_o.a_ready Yes Yes T4,T366,T49 Yes T4,T366,T49 OUTPUT
tl_o.d_error Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T366,T273 Yes T4,T366,T273 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T366,T49 Yes T4,T366,T49 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T366,T49 Yes T4,T366,T49 OUTPUT
tl_o.d_sink Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T73,*T78,*T118 Yes T73,T75,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T366,*T49 Yes T4,T366,T49 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T366,T49 Yes T4,T366,T49 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
alert_rx_i[0].ack_p Yes Yes T275,T339,T254 Yes T275,T339,T254 INPUT
alert_rx_i[0].ping_n Yes Yes T150,T81,T82 Yes T150,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T150,T81,T82 Yes T150,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T1,T5 Yes T4,T1,T5 OUTPUT
alert_tx_o[0].alert_p Yes Yes T275,T339,T254 Yes T275,T339,T254 OUTPUT
cio_rx_i Yes Yes T4,T15,T38 Yes T4,T1,T5 INPUT
cio_tx_o Yes Yes T4,T49,T50 Yes T4,T49,T50 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T4,T112,T207 Yes T4,T112,T207 OUTPUT
intr_tx_empty_o Yes Yes T4,T112,T207 Yes T4,T112,T207 OUTPUT
intr_rx_watermark_o Yes Yes T4,T112,T207 Yes T4,T112,T207 OUTPUT
intr_tx_done_o Yes Yes T4,T112,T207 Yes T4,T112,T207 OUTPUT
intr_rx_overflow_o Yes Yes T4,T112,T207 Yes T4,T112,T207 OUTPUT
intr_rx_frame_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_break_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_timeout_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_parity_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 40 40 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
rst_ni Yes Yes T15,T59,T38 Yes T4,T1,T5 INPUT
tl_i.d_ready Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T366,T53,T49 Yes T366,T53,T49 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T366,T53,T49 Yes T366,T53,T49 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[5:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T65,*T2,*T76 Yes T65,T2,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T65,T2,T77 Yes T65,T2,T77 INPUT
tl_i.a_valid Yes Yes T366,T53,T49 Yes T366,T53,T49 INPUT
tl_o.a_ready Yes Yes T366,T49,T273 Yes T366,T49,T273 OUTPUT
tl_o.d_error Yes Yes T73,T78,T118 Yes T73,T78,T118 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T366,T273,T379 Yes T366,T273,T379 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T366,T49,T273 Yes T366,T49,T273 OUTPUT
tl_o.d_data[31:0] Yes Yes T366,T49,T273 Yes T366,T49,T273 OUTPUT
tl_o.d_sink Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T73,*T78,*T118 Yes T73,T75,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T366,*T49,*T273 Yes T366,T49,T273 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T366,T49,T273 Yes T366,T49,T273 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
alert_rx_i[0].ack_p Yes Yes T339,T239,T150 Yes T339,T239,T150 INPUT
alert_rx_i[0].ping_n Yes Yes T150,T81,T82 Yes T150,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T150,T81,T82 Yes T150,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T1,T5 Yes T4,T1,T5 OUTPUT
alert_tx_o[0].alert_p Yes Yes T339,T239,T150 Yes T339,T239,T150 OUTPUT
cio_rx_i Yes Yes T15,T38,T39 Yes T4,T1,T5 INPUT
cio_tx_o Yes Yes T49,T50,T51 Yes T49,T50,T51 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T379,T210,T267 Yes T379,T210,T267 OUTPUT
intr_tx_empty_o Yes Yes T210,T267,T318 Yes T210,T267,T318 OUTPUT
intr_rx_watermark_o Yes Yes T210,T267,T318 Yes T210,T267,T318 OUTPUT
intr_tx_done_o Yes Yes T323,T324,T210 Yes T323,T324,T210 OUTPUT
intr_rx_overflow_o Yes Yes T323,T324,T210 Yes T323,T324,T210 OUTPUT
intr_rx_frame_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_break_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_timeout_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_parity_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
rst_ni Yes Yes T15,T59,T38 Yes T4,T1,T5 INPUT
tl_i.d_ready Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T112,T207,T317 Yes T112,T207,T317 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T112,T207,T317 Yes T112,T207,T317 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[5:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T65,*T2,*T76 Yes T65,T2,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T65,T2,T77 Yes T65,T2,T77 INPUT
tl_i.a_valid Yes Yes T112,T207,T317 Yes T112,T207,T317 INPUT
tl_o.a_ready Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
tl_o.d_error Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
tl_o.d_data[31:0] Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
tl_o.d_sink Yes Yes T73,T75,T78 Yes T73,T78,T118 OUTPUT
tl_o.d_source[5:0] Yes Yes *T78,*T118,*T225 Yes T73,T78,T118 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T78 Yes T73,T74,T78 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T112,*T207,*T317 Yes T112,T207,T317 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
alert_rx_i[0].ack_p Yes Yes T254,T349,T81 Yes T254,T349,T81 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T1,T5 Yes T4,T1,T5 OUTPUT
alert_tx_o[0].alert_p Yes Yes T254,T349,T81 Yes T254,T349,T81 OUTPUT
cio_rx_i Yes Yes T112,T207,T317 Yes T22,T112,T207 INPUT
cio_tx_o Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
intr_tx_empty_o Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
intr_rx_watermark_o Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
intr_tx_done_o Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
intr_rx_overflow_o Yes Yes T112,T207,T317 Yes T112,T207,T317 OUTPUT
intr_rx_frame_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_break_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_timeout_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_parity_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
rst_ni Yes Yes T15,T59,T38 Yes T4,T1,T5 INPUT
tl_i.d_ready Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T113,T319 Yes T4,T113,T319 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T113,T319 Yes T4,T113,T319 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[5:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T65,*T2,*T76 Yes T65,T2,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T65,T2,T77 Yes T65,T2,T77 INPUT
tl_i.a_valid Yes Yes T4,T113,T319 Yes T4,T113,T319 INPUT
tl_o.a_ready Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
tl_o.d_error Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
tl_o.d_sink Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T73,*T78,*T118 Yes T73,T75,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T113,*T319 Yes T4,T113,T319 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
alert_rx_i[0].ack_p Yes Yes T82,T83,T148 Yes T82,T83,T148 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T148 Yes T82,T83,T148 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T148 Yes T82,T83,T148 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T1,T5 Yes T4,T1,T5 OUTPUT
alert_tx_o[0].alert_p Yes Yes T82,T83,T148 Yes T82,T83,T148 OUTPUT
cio_rx_i Yes Yes T4,T113,T319 Yes T4,T113,T319 INPUT
cio_tx_o Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
intr_tx_empty_o Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
intr_rx_watermark_o Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
intr_tx_done_o Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
intr_rx_overflow_o Yes Yes T4,T113,T319 Yes T4,T113,T319 OUTPUT
intr_rx_frame_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_break_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_timeout_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_parity_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
rst_ni Yes Yes T15,T59,T38 Yes T4,T1,T5 INPUT
tl_i.d_ready Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T24,T25,T307 Yes T24,T25,T307 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T24,T25,T307 Yes T24,T25,T307 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[5:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T1,*T5 Yes T4,T1,T5 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T65,*T2,*T76 Yes T65,T2,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T65,T2,T77 Yes T65,T2,T77 INPUT
tl_i.a_valid Yes Yes T24,T25,T307 Yes T24,T25,T307 INPUT
tl_o.a_ready Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
tl_o.d_error Yes Yes T73,T75,T78 Yes T75,T78,T118 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
tl_o.d_data[31:0] Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
tl_o.d_sink Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T78,*T118,*T225 Yes T73,T75,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T24,*T25,*T307 Yes T24,T25,T307 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T1,T5 Yes T4,T1,T5 INPUT
alert_rx_i[0].ack_p Yes Yes T275,T659,T81 Yes T275,T659,T81 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T1,T5 Yes T4,T1,T5 OUTPUT
alert_tx_o[0].alert_p Yes Yes T275,T659,T81 Yes T275,T659,T81 OUTPUT
cio_rx_i Yes Yes T24,T25,T307 Yes T24,T25,T307 INPUT
cio_tx_o Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
intr_tx_empty_o Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
intr_rx_watermark_o Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
intr_tx_done_o Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
intr_rx_overflow_o Yes Yes T24,T25,T307 Yes T24,T25,T307 OUTPUT
intr_rx_frame_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_break_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_timeout_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT
intr_rx_parity_err_o Yes Yes T306,T310,T311 Yes T306,T310,T311 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%