dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_alert_test

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_invert_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_virtual_od_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_select_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_keeper_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_schmitt_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_od_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_input_disable_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_slew_rate_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_drive_strength_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_invert_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_virtual_od_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_select_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_keeper_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_schmitt_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_od_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_input_disable_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_slew_rate_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_drive_strength_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_invert_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_virtual_od_en_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_en_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_select_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_keeper_en_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_schmitt_en_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_od_en_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_input_disable_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_slew_rate_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_drive_strength_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_invert_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_virtual_od_en_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_pull_en_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_pull_select_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_keeper_en_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_schmitt_en_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_od_en_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_input_disable_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_slew_rate_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_drive_strength_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_invert_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_virtual_od_en_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_pull_en_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_pull_select_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_keeper_en_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_schmitt_en_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_od_en_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_input_disable_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_slew_rate_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_drive_strength_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_invert_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_virtual_od_en_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_pull_en_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_pull_select_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_keeper_en_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_schmitt_en_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_od_en_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_input_disable_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_slew_rate_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_drive_strength_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_invert_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_virtual_od_en_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_pull_en_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_pull_select_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_keeper_en_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_schmitt_en_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_od_en_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_input_disable_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_slew_rate_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_drive_strength_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_invert_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_virtual_od_en_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_pull_en_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_pull_select_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_keeper_en_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_schmitt_en_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_od_en_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_input_disable_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_slew_rate_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_drive_strength_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_invert_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_virtual_od_en_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_pull_en_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_pull_select_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_keeper_en_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_schmitt_en_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_od_en_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_input_disable_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_slew_rate_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_drive_strength_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_invert_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_virtual_od_en_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_pull_en_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_pull_select_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_keeper_en_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_schmitt_en_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_od_en_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_input_disable_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_slew_rate_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_drive_strength_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_invert_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_virtual_od_en_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_pull_en_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_pull_select_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_keeper_en_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_schmitt_en_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_od_en_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_input_disable_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_slew_rate_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_drive_strength_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_invert_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_virtual_od_en_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_pull_en_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_pull_select_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_keeper_en_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_schmitt_en_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_od_en_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_input_disable_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_slew_rate_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_drive_strength_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_invert_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_virtual_od_en_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_pull_en_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_pull_select_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_keeper_en_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_schmitt_en_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_od_en_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_input_disable_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_slew_rate_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_drive_strength_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_invert_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_virtual_od_en_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_pull_en_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_pull_select_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_keeper_en_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_schmitt_en_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_od_en_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_input_disable_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_slew_rate_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_drive_strength_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_invert_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_virtual_od_en_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_pull_en_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_pull_select_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_keeper_en_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_schmitt_en_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_od_en_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_input_disable_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_slew_rate_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_drive_strength_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_invert_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_virtual_od_en_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_pull_en_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_pull_select_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_keeper_en_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_schmitt_en_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_od_en_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_input_disable_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_slew_rate_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_drive_strength_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_invert_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_virtual_od_en_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_pull_en_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_pull_select_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_keeper_en_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_schmitt_en_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_od_en_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_input_disable_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_slew_rate_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_drive_strength_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_invert_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_virtual_od_en_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_pull_en_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_pull_select_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_keeper_en_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_schmitt_en_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_od_en_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_input_disable_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_slew_rate_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_drive_strength_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_invert_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_virtual_od_en_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_pull_en_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_pull_select_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_keeper_en_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_schmitt_en_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_od_en_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_input_disable_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_slew_rate_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_drive_strength_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_invert_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_virtual_od_en_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_pull_en_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_pull_select_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_keeper_en_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_schmitt_en_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_od_en_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_input_disable_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_slew_rate_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_drive_strength_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_invert_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_virtual_od_en_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_pull_en_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_pull_select_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_keeper_en_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_schmitt_en_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_od_en_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_input_disable_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_slew_rate_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_drive_strength_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_invert_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_virtual_od_en_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_pull_en_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_pull_select_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_keeper_en_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 99.72 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_alert_test
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_invert_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_virtual_od_en_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_en_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_select_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_keeper_en_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_schmitt_en_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_od_en_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_input_disable_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_slew_rate_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_drive_strength_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_invert_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_virtual_od_en_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_en_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_select_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_keeper_en_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_schmitt_en_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_od_en_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_input_disable_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_slew_rate_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_drive_strength_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_invert_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_virtual_od_en_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_en_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_select_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_keeper_en_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_schmitt_en_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_od_en_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_input_disable_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_slew_rate_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_drive_strength_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_invert_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_virtual_od_en_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_pull_en_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_pull_select_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_keeper_en_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_schmitt_en_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_od_en_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_input_disable_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_slew_rate_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_drive_strength_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_invert_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_virtual_od_en_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_pull_en_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_pull_select_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_keeper_en_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_schmitt_en_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_od_en_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_input_disable_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_slew_rate_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_drive_strength_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_invert_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_virtual_od_en_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_pull_en_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_pull_select_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_keeper_en_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_schmitt_en_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_od_en_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_input_disable_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_slew_rate_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_drive_strength_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_invert_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_virtual_od_en_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_pull_en_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_pull_select_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_keeper_en_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_schmitt_en_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_od_en_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_input_disable_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_slew_rate_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_drive_strength_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_invert_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_virtual_od_en_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_pull_en_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_pull_select_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_keeper_en_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_schmitt_en_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_od_en_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_input_disable_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_slew_rate_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_drive_strength_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_invert_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_virtual_od_en_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_pull_en_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_pull_select_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_keeper_en_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_schmitt_en_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_od_en_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_input_disable_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_slew_rate_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_drive_strength_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_invert_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_virtual_od_en_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_pull_en_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_pull_select_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_keeper_en_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_schmitt_en_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_od_en_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_input_disable_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_slew_rate_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_drive_strength_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_invert_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_virtual_od_en_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_pull_en_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_pull_select_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_keeper_en_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_schmitt_en_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_od_en_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_input_disable_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_slew_rate_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_drive_strength_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_invert_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_virtual_od_en_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_pull_en_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_pull_select_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_keeper_en_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_schmitt_en_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_od_en_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_input_disable_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_slew_rate_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_drive_strength_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_invert_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_virtual_od_en_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_pull_en_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_pull_select_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_keeper_en_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_schmitt_en_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_od_en_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_input_disable_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_slew_rate_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_drive_strength_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_invert_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_virtual_od_en_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_pull_en_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_pull_select_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_keeper_en_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_schmitt_en_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_od_en_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_input_disable_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_slew_rate_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_drive_strength_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_invert_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_virtual_od_en_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_pull_en_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_pull_select_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_keeper_en_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_schmitt_en_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_od_en_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_input_disable_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_slew_rate_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_drive_strength_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_invert_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_virtual_od_en_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_pull_en_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_pull_select_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_keeper_en_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_schmitt_en_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_od_en_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_input_disable_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_slew_rate_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_drive_strength_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_invert_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_virtual_od_en_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_pull_en_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_pull_select_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_keeper_en_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_schmitt_en_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_od_en_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_input_disable_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_slew_rate_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_drive_strength_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_invert_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_virtual_od_en_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_pull_en_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_pull_select_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_keeper_en_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_schmitt_en_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_od_en_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_input_disable_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_slew_rate_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_drive_strength_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_invert_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_virtual_od_en_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_pull_en_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_pull_select_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_keeper_en_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_schmitt_en_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_od_en_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_input_disable_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_slew_rate_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_drive_strength_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_invert_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_virtual_od_en_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_pull_en_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_pull_select_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_keeper_en_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_schmitt_en_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_od_en_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_input_disable_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_slew_rate_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_drive_strength_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_invert_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_virtual_od_en_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_pull_en_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_pull_select_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_keeper_en_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_schmitt_en_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_od_en_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_input_disable_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_slew_rate_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_drive_strength_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_invert_21
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_virtual_od_en_21
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_pull_en_21
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_pull_select_21
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_keeper_en_21
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_alert_test
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_invert_0
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_virtual_od_en_0
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_en_0
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_select_0
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_keeper_en_0
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_schmitt_en_0
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_od_en_0
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_input_disable_0
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_slew_rate_0
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_drive_strength_0
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_invert_1
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_virtual_od_en_1
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_en_1
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_select_1
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_keeper_en_1
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_schmitt_en_1
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_od_en_1
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_input_disable_1
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_slew_rate_1
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_drive_strength_1
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_invert_2
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_virtual_od_en_2
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_en_2
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_select_2
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_keeper_en_2
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_schmitt_en_2
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_od_en_2
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_input_disable_2
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_slew_rate_2
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_drive_strength_2
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_invert_3
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_virtual_od_en_3
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_pull_en_3
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_pull_select_3
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_keeper_en_3
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_schmitt_en_3
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_od_en_3
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_input_disable_3
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_slew_rate_3
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_drive_strength_3
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_invert_4
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_virtual_od_en_4
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_pull_en_4
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_pull_select_4
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_keeper_en_4
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_schmitt_en_4
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_od_en_4
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_input_disable_4
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_slew_rate_4
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_4_drive_strength_4
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_invert_5
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_virtual_od_en_5
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_pull_en_5
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_pull_select_5
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_keeper_en_5
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_schmitt_en_5
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_od_en_5
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_input_disable_5
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_slew_rate_5
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_5_drive_strength_5
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_invert_6
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_virtual_od_en_6
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_pull_en_6
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_pull_select_6
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_keeper_en_6
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_schmitt_en_6
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_od_en_6
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_input_disable_6
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_slew_rate_6
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_6_drive_strength_6
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_invert_7
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_virtual_od_en_7
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_pull_en_7
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_pull_select_7
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_keeper_en_7
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_schmitt_en_7
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_od_en_7
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_input_disable_7
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_slew_rate_7
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_7_drive_strength_7
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_invert_8
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_virtual_od_en_8
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_pull_en_8
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_pull_select_8
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_keeper_en_8
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_schmitt_en_8
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_od_en_8
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_input_disable_8
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_slew_rate_8
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_8_drive_strength_8
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_invert_9
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_virtual_od_en_9
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_pull_en_9
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_pull_select_9
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_keeper_en_9
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_schmitt_en_9
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_od_en_9
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_input_disable_9
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_slew_rate_9
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_9_drive_strength_9
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_invert_10
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_virtual_od_en_10
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_pull_en_10
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_pull_select_10
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_keeper_en_10
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_schmitt_en_10
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_od_en_10
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_input_disable_10
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_slew_rate_10
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_10_drive_strength_10
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_invert_11
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_virtual_od_en_11
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_pull_en_11
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_pull_select_11
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_keeper_en_11
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_schmitt_en_11
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_od_en_11
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_input_disable_11
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_slew_rate_11
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_11_drive_strength_11
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_invert_12
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_virtual_od_en_12
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_pull_en_12
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_pull_select_12
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_keeper_en_12
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_schmitt_en_12
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_od_en_12
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_input_disable_12
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_slew_rate_12
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_12_drive_strength_12
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_invert_13
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_virtual_od_en_13
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_pull_en_13
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_pull_select_13
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_keeper_en_13
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_schmitt_en_13
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_od_en_13
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_input_disable_13
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_slew_rate_13
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_13_drive_strength_13
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_invert_14
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_virtual_od_en_14
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_pull_en_14
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_pull_select_14
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_keeper_en_14
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_schmitt_en_14
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_od_en_14
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_input_disable_14
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_slew_rate_14
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_14_drive_strength_14
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_invert_15
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_virtual_od_en_15
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_pull_en_15
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_pull_select_15
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_keeper_en_15
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_schmitt_en_15
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_od_en_15
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_input_disable_15
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_slew_rate_15
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_15_drive_strength_15
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_invert_16
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_virtual_od_en_16
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_pull_en_16
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_pull_select_16
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_keeper_en_16
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_schmitt_en_16
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_od_en_16
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_input_disable_16
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_slew_rate_16
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_16_drive_strength_16
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_invert_17
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_virtual_od_en_17
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_pull_en_17
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_pull_select_17
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_keeper_en_17
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_schmitt_en_17
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_od_en_17
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_input_disable_17
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_slew_rate_17
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_17_drive_strength_17
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_invert_18
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_virtual_od_en_18
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_pull_en_18
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_pull_select_18
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_keeper_en_18
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_schmitt_en_18
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_od_en_18
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_input_disable_18
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_slew_rate_18
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_18_drive_strength_18
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_invert_19
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_virtual_od_en_19
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_pull_en_19
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_pull_select_19
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_keeper_en_19
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_schmitt_en_19
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_od_en_19
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_input_disable_19
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_slew_rate_19
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_19_drive_strength_19
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_invert_20
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_virtual_od_en_20
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_pull_en_20
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_pull_select_20
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_keeper_en_20
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_schmitt_en_20
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_od_en_20
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_input_disable_20
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_slew_rate_20
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_20_drive_strength_20
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_invert_21
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_virtual_od_en_21
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_pull_en_21
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_pull_select_21
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_21_keeper_en_21
Line No.TotalCoveredPercent
TOTAL5360.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 1 1
29 1 1
30 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%