Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
clk_fixed_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
clk_usb_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
clk_spi_host0_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
clk_spi_host1_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_main_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
rst_fixed_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
rst_usb_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
rst_spi_host0_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
rst_spi_host1_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T38,T188,T96	Yes	T38,T188,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T38,T188,T96	Yes	T38,T188,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T77,T194,T195	Yes	T77,T194,T195	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T77,T194,T195	Yes	T77,T194,T195	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T15,T38,T188	Yes	T15,T38,T188	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T65,T2,T76	Yes	T65,T2,T76	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T65,T2,T76	Yes	T65,T2,T76	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T65,T2,T76	Yes	T65,T2,T76	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T65,T2,T76	Yes	T65,T2,T76	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T2,T66	Yes	T65,T2,T66	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T65,T2,T76	Yes	T65,T2,T76	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T65,T2,T76	Yes	T65,T2,T76	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T2,T73,T75	Yes	T2,T73,T75	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T2,T75,T78	Yes	T2,T73,T75	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T2,*T73,*T74	Yes	T2,T73,T74	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T2,T73,T74	Yes	T2,T73,T74	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T76,*T233,*T234	Yes	T76,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T76,T233,T234	Yes	T76,T233,T234	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T76,*T233,*T234	Yes	T76,T233,T234	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T15,T59,T38	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T2,T76,T233	Yes	T2,T76,T233	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T49,T158,T65	Yes	T49,T158,T65	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T49,T158,T65	Yes	T49,T158,T65	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T73,*T75,*T78	Yes	T73,T75,T78	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T54,T55	Yes	T2,T54,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T385,T386	Yes	T2,T385,T386	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T385,T386	Yes	T2,T385,T386	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T2,T54,T55	Yes	T2,T54,T55	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T2,T385,T386	Yes	T2,T385,T386	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T2,T385,T386	Yes	T2,T385,T386	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T2,T385,T386	Yes	T2,T385,T386	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T385,T387,T388	Yes	T385,T387,T388	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T73,T74	Yes	T2,T54,T55	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T2,T385,T387	Yes	T2,T385,T54	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T2,T73,*T78	Yes	T2,T73,T75	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T2,*T386,*T389	Yes	T2,T385,T386	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T2,T385,T386	Yes	T2,T385,T386	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_peri_i.d_error	Yes	Yes	T38,T39,T188	Yes	T38,T39,T188	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_peri_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T21,T23,T193	Yes	T21,T23,T193	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T75	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T2,*T21,*T22	Yes	T2,T21,T22	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T2,T41,T42	Yes	T2,T41,T42	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T2,T41,T42	Yes	T2,T41,T42	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T2,T41,T42	Yes	T2,T41,T42	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T2,T41,T42	Yes	T2,T41,T42	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T78,T118	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T78	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T2,*T41,*T379	Yes	T2,T41,T379	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T2,T41,T379	Yes	T2,T41,T379	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T75,*T78,*T118	Yes	T75,T78,T118	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	INPUT
tl_usbdev_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T27,T379,T306	Yes	T27,T85,T379	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T85,T379	Yes	T27,T379,T306	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T78	Yes	T73,T75,T78	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T3,*T26,*T27	Yes	T3,T26,T27	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T78	Yes	T77,T73,T78	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T77,T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T75,T78,T118	Yes	T75,T78,T118	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T77,T75,T78	Yes	T77,T73,T75	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T73,*T75,*T78	Yes	T73,T75,T78	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_hmac_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T232,T49,T675	Yes	T232,T49,T675	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T232,T49,T675	Yes	T232,T49,T675	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T232,T49,T675	Yes	T232,T49,T675	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T675,T309,T336	Yes	T675,T309,T336	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	INPUT
tl_hmac_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T232,T49,T675	Yes	T232,T49,T675	INPUT
tl_hmac_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T232,*T49,*T675	Yes	T232,T49,T675	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T232,T49,T412	Yes	T232,T49,T412	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T15,T59	Yes	T4,T1,T5	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T5,T411,T279	Yes	T5,T411,T279	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T5,T411,T279	Yes	T5,T411,T279	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T77,*T79,*T73	Yes	T77,T79,T73	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T5,T411,T279	Yes	T5,T411,T279	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	INPUT
tl_kmac_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T78,T118	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T5,T107,T411	Yes	T5,T411,T413	INPUT
tl_kmac_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T78	Yes	T77,T79,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T5,*T107,*T411	Yes	T5,T411,T157	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T5,T412,T107	Yes	T5,T412,T107	INPUT
tl_aes_o.d_ready	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T108,T635,T636	Yes	T108,T635,T636	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T108,T635,T636	Yes	T108,T635,T636	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T87,T108,T412	Yes	T87,T108,T412	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T108,T635,T636	Yes	T108,T635,T636	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T87,T108,T412	Yes	T87,T108,T412	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T73,*T75,*T78	Yes	T73,T75,T78	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T87,T108,T412	Yes	T87,T108,T412	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T87,T108,T635	Yes	T87,T108,T635	INPUT
tl_aes_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T78,T118	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T87,T108,T635	Yes	T87,T108,T635	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T108,T635	Yes	T87,T108,T635	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T87,T108,T635	Yes	T87,T108,T635	INPUT
tl_aes_i.d_sink	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T118	Yes	T73,T75,T78	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T75	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T87,*T108,*T635	Yes	T87,T108,T635	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T87,T108,T635	Yes	T87,T108,T635	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T78,T118	Yes	T73,T75,T78	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T78,T118	Yes	T73,T75,T78	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T118	Yes	T77,T73,T75	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T87,*T232,*T106	Yes	T87,T232,T49	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_csrng_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	INPUT
tl_csrng_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T118	Yes	T77,T73,T75	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T87,*T232,*T106	Yes	T87,T232,T106	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_edn0_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	INPUT
tl_edn0_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T78	Yes	T77,T73,T75	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T87,*T232,*T106	Yes	T87,T232,T106	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_edn1_o.d_ready	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_edn1_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_edn1_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T77,*T75,*T78	Yes	T77,T73,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T87,*T232,*T106	Yes	T87,T232,T106	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T87,T232,T106	Yes	T87,T232,T106	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T1,T15	Yes	T4,T1,T5	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T15	Yes	T4,T1,T15	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T1,T15	Yes	T4,T1,T15	INPUT
tl_otbn_o.d_ready	Yes	Yes	T15,T87,T59	Yes	T4,T1,T5	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T87,T49,T106	Yes	T87,T49,T106	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T87,T49,T106	Yes	T87,T49,T106	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T65,*T194,*T195	Yes	T65,T194,T195	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	INPUT
tl_otbn_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T87,T49,T106	Yes	T87,T49,T106	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	INPUT
tl_otbn_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T65,*T194,*T195	Yes	T65,T194,T195	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T87,*T49,*T106	Yes	T87,T49,T106	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T87,T49,T412	Yes	T87,T49,T412	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	INPUT
tl_keymgr_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T53,T181,T107	Yes	T53,T181,T107	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T78,T118,T278	Yes	T75,T78,T118	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T118	Yes	T77,T73,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T74,T78,T118	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T53,*T49,*T181	Yes	T53,T49,T181	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T53,T49,T181	Yes	T53,T49,T181	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T2,T74,T75	Yes	T2,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T15,T86	Yes	T1,T15,T86	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T15,T86	Yes	T1,T15,T86	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T2,*T73,*T75	Yes	T2,T73,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T2,T176,T177	Yes	T2,T176,T177	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T111,T168	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T2,T111,T168	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T2,*T73,*T78	Yes	T2,T73,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T2,*T111,*T168	Yes	T2,T401,T111	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range