Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_peri_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_main_o.d_error	Yes	Yes	T38,T39,T188	Yes	T38,T39,T188	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_main_o.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T366,T53,T49	Yes	T366,T53,T49	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T366,T53,T49	Yes	T366,T53,T49	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T366,T53,T49	Yes	T366,T53,T49	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T366,T49,T273	Yes	T366,T49,T273	INPUT
tl_uart0_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T366,T273,T379	Yes	T366,T273,T379	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T366,T49,T273	Yes	T366,T49,T273	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T366,T49,T273	Yes	T366,T49,T273	INPUT
tl_uart0_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T118	Yes	T73,T75,T78	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T366,*T49,*T273	Yes	T366,T49,T273	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T366,T49,T273	Yes	T366,T49,T273	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	INPUT
tl_uart1_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	INPUT
tl_uart1_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T78,T118	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T78,*T118,*T225	Yes	T73,T78,T118	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T112,*T207,*T317	Yes	T112,T207,T317	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T112,T207,T317	Yes	T112,T207,T317	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	INPUT
tl_uart2_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	INPUT
tl_uart2_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T118	Yes	T73,T75,T78	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T4,*T113,*T319	Yes	T4,T113,T319	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T4,T113,T319	Yes	T4,T113,T319	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	INPUT
tl_uart3_i.d_error	Yes	Yes	T73,T75,T78	Yes	T75,T78,T118	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	INPUT
tl_uart3_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T78,*T118,*T225	Yes	T73,T75,T78	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T24,*T25,*T307	Yes	T24,T25,T307	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T24,T25,T307	Yes	T24,T25,T307	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	INPUT
tl_i2c0_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T75	Yes	T77,T73,T75	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T232,*T308,*T206	Yes	T232,T308,T206	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T232,T308,T206	Yes	T232,T308,T206	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	INPUT
tl_i2c1_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T78	Yes	T77,T73,T75	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T232,*T308,*T77	Yes	T232,T308,T77	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T232,T308,T77	Yes	T232,T308,T77	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	INPUT
tl_i2c2_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T118	Yes	T77,T73,T75	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T74,T78,T118	Yes	T73,T74,T78	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T232,*T208,*T209	Yes	T232,T208,T209	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T232,T208,T209	Yes	T232,T208,T209	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	INPUT
tl_pattgen_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T79,T78,*T118	Yes	T79,T73,T75	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T86,*T144,*T145	Yes	T86,T144,T145	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T86,T144,T145	Yes	T86,T144,T145	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T2,T73,*T75	Yes	T2,T73,T75	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T2,*T104,*T212	Yes	T2,T104,T212	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T2,T104,T212	Yes	T2,T104,T212	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_gpio_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T232,T308,T32	Yes	T232,T308,T32	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T232,T308,T32	Yes	T1,T232,T104	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T232,T308,T32	Yes	T1,T232,T104	INPUT
tl_gpio_i.d_sink	Yes	Yes	T75,T78,T118	Yes	T73,T75,T78	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T118	Yes	T77,T73,T75	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T75	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T15,*T59	Yes	T4,T1,T5	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	INPUT
tl_spi_device_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T2,*T73,*T78	Yes	T2,T73,T75	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T2,*T21,*T23	Yes	T2,T21,T23	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T2,T21,T23	Yes	T2,T21,T23	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T2,*T73,*T78	Yes	T2,T73,T75	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T2,*T230,*T243	Yes	T2,T230,T243	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T2,T230,T243	Yes	T2,T230,T243	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T73,T75,T78	Yes	T75,T78,T118	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T75,T78,T118	Yes	T75,T78,T118	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T75	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T15,*T59	Yes	T1,T15,T59	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T1,T15,T59	Yes	T1,T15,T59	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T75	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T89,T53	Yes	T4,T89,T53	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T89,T108	Yes	T4,T89,T108	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T89,T109	Yes	T4,T89,T109	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T15,T38	Yes	T4,T1,T5	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T15,T38	Yes	T4,T1,T5	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T78,T118	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T118	Yes	T73,T75,T78	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T89,*T53	Yes	T4,T89,T53	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T2,*T79,*T73	Yes	T2,T79,T73	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T137,*T141,*T142	Yes	T137,T141,T142	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T60,*T107,*T143	Yes	T60,T107,T143	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T79,T73,T74	Yes	T79,T73,T74	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T79,T73,T74	Yes	T79,T73,T74	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T79,T73,T74	Yes	T79,T73,T74	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T79,T73,T74	Yes	T79,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T73,T74	Yes	T79,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T15,T59,T38	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T79,T73,T78	Yes	T79,T73,T75	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T15,T59,T38	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T79,T73,T74	Yes	T79,T73,T74	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T52,T60	Yes	T17,T52,T60	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T76,*T298,*T299	Yes	T76,T298,T299	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T17,*T52,*T60	Yes	T17,T52,T49	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T17,T52,T49	Yes	T17,T52,T49	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T59,T122,T2	Yes	T59,T122,T2	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T122,T2	Yes	T59,T122,T2	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T75	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T15,*T59,*T38	Yes	T4,T1,T5	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T73,*T75,*T78	Yes	T73,T75,T78	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T15,*T88,*T38	Yes	T15,T88,T38	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T2,T111,T168	Yes	T2,T111,T168	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T111,T168	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T2,T111,T168	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T118	Yes	T2,T73,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T2,*T111,*T168	Yes	T2,T401,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T49,T2,T50	Yes	T49,T2,T50	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T15,T59,T88	Yes	T15,T59,T88	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T1,T5	Yes	T15,T38,T39	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T65,*T194,*T195	Yes	T65,T194,T195	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T5	Yes	T4,T1,T5	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T75,T78,T118	Yes	T73,T75,T78	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T118	Yes	T234,T73,T75	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T78	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T15,*T88,*T38	Yes	T15,T88,T38	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T15,T88,T38	Yes	T15,T88,T38	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T75,T78,T118	Yes	T75,T78,T118	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T2,T198,T419	Yes	T2,T3,T198	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T2,*T75,*T78	Yes	T2,T73,T75	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T198	Yes	T2,T3,T198	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T2,T3,T198	Yes	T2,T3,T198	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T3,T103,T104	Yes	T232,T3,T103	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T78,*T118,*T278	Yes	T73,T75,T78	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T232,*T3,*T103	Yes	T232,T3,T103	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T232,T3,T103	Yes	T232,T3,T103	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T65,*T2,*T76	Yes	T65,T2,T76	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T65,T2,T77	Yes	T65,T2,T77	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
tl_ast_i.d_error	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
tl_ast_i.d_sink	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T73,T78,T118	Yes	T73,T78,T118	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T73,T78,T118	Yes	T73,T75,T78	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T73,*T78,*T118	Yes	T73,T78,T118	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range