Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.41 99.34 100.00 98.31 100.00 u_pinmux_strap_sampling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 980 980 0 0
OutputsKnown_A 117250470 116586953 0 0
gen_no_flops.OutputDelay_A 117250470 116586953 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 980 980 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T59 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117250470 116586953 0 0
T1 31246 30561 0 0
T4 52075 51758 0 0
T5 17214 16947 0 0
T15 363682 362229 0 0
T38 57571 56886 0 0
T59 45088 44482 0 0
T86 19073 18293 0 0
T87 303595 303073 0 0
T88 39814 39084 0 0
T89 54816 54395 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117250470 116586953 0 0
T1 31246 30561 0 0
T4 52075 51758 0 0
T5 17214 16947 0 0
T15 363682 362229 0 0
T38 57571 56886 0 0
T59 45088 44482 0 0
T86 19073 18293 0 0
T87 303595 303073 0 0
T88 39814 39084 0 0
T89 54816 54395 0 0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 980 980 0 0
OutputsKnown_A 117250470 116586953 0 0
gen_no_flops.OutputDelay_A 117250470 116586953 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 980 980 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T59 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117250470 116586953 0 0
T1 31246 30561 0 0
T4 52075 51758 0 0
T5 17214 16947 0 0
T15 363682 362229 0 0
T38 57571 56886 0 0
T59 45088 44482 0 0
T86 19073 18293 0 0
T87 303595 303073 0 0
T88 39814 39084 0 0
T89 54816 54395 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117250470 116586953 0 0
T1 31246 30561 0 0
T4 52075 51758 0 0
T5 17214 16947 0 0
T15 363682 362229 0 0
T38 57571 56886 0 0
T59 45088 44482 0 0
T86 19073 18293 0 0
T87 303595 303073 0 0
T88 39814 39084 0 0
T89 54816 54395 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%