Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_invert_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T11
1	-	Covered	T1,T11,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	116088	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	293	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	116088	0	0
T1	31246	765	0	0
T2	0	370	0	0
T5	17214	0	0	0
T11	0	766	0	0
T12	0	789	0	0
T15	363682	0	0	0
T38	57571	0	0	0
T59	45088	0	0	0
T74	0	595	0	0
T86	19073	0	0	0
T87	303595	0	0	0
T88	39814	0	0	0
T89	54816	0	0	0
T102	116201	0	0	0
T138	0	917	0	0
T139	0	1929	0	0
T367	0	1966	0	0
T368	0	5953	0	0
T390	0	470	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	293	0	0
T1	31246	2	0	0
T2	0	1	0	0
T5	17214	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T15	363682	0	0	0
T38	57571	0	0	0
T59	45088	0	0	0
T74	0	2	0	0
T86	19073	0	0	0
T87	303595	0	0	0
T88	39814	0	0	0
T89	54816	0	0	0
T102	116201	0	0	0
T138	0	2	0	0
T139	0	5	0	0
T367	0	5	0	0
T368	0	15	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T13,T74

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T13,T74
1	1	Covered	T2,T13,T74

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T74
1	-	Covered	T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T13,T74

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T74
1	1	Covered	T2,T13,T74

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T13,T74
0	0	1	Covered	T2,T13,T74
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T13,T74
0	0	1	Covered	T2,T13,T74
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	99849	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	253	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	99849	0	0
T2	484077	382	0	0
T3	130393	0	0	0
T13	0	932	0	0
T74	0	627	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	895	0	0
T139	0	1181	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	816	0	0
T368	0	3659	0	0
T380	0	729	0	0
T390	0	427	0	0
T391	0	2684	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	253	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T13	0	2	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	3	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2	0	0
T368	0	9	0	0
T380	0	2	0	0
T390	0	1	0	0
T391	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T74,T138
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	99719	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	253	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	99719	0	0
T2	484077	391	0	0
T3	130393	0	0	0
T74	0	602	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	883	0	0
T139	0	1994	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	1487	0	0
T368	0	6329	0	0
T380	0	633	0	0
T382	0	1581	0	0
T390	0	470	0	0
T391	0	3533	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	253	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	5	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	4	0	0
T368	0	16	0	0
T380	0	2	0	0
T382	0	4	0	0
T390	0	1	0	0
T391	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T74,T138
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	99430	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	251	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	99430	0	0
T2	484077	393	0	0
T3	130393	0	0	0
T74	0	547	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	843	0	0
T139	0	1163	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	1148	0	0
T368	0	2390	0	0
T380	0	692	0	0
T382	0	7141	0	0
T390	0	378	0	0
T391	0	1951	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	251	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	3	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	3	0	0
T368	0	6	0	0
T380	0	2	0	0
T382	0	17	0	0
T390	0	1	0	0
T391	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T74,T138
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	105814	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	266	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	105814	0	0
T2	484077	395	0	0
T3	130393	0	0	0
T74	0	661	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	866	0	0
T139	0	4393	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2018	0	0
T368	0	5202	0	0
T380	0	734	0	0
T382	0	5212	0	0
T390	0	447	0	0
T391	0	1926	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	266	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	11	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	5	0	0
T368	0	13	0	0
T380	0	2	0	0
T382	0	12	0	0
T390	0	1	0	0
T391	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T3,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T8
1	-	Covered	T3,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T3,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	129920	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	326	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	129920	0	0
T2	484077	431	0	0
T3	130393	1408	0	0
T8	0	905	0	0
T9	0	1546	0	0
T10	0	883	0	0
T57	0	1041	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T99	0	649	0	0
T100	0	741	0	0
T101	0	623	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T392	0	778	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	326	0	0
T2	484077	1	0	0
T3	130393	4	0	0
T8	0	2	0	0
T9	0	4	0	0
T10	0	2	0	0
T57	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T392	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T74,T138
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	93494	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	239	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	93494	0	0
T2	484077	418	0	0
T3	130393	0	0	0
T74	0	685	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	794	0	0
T139	0	2814	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	374	0	0
T368	0	4814	0	0
T380	0	726	0	0
T382	0	1603	0	0
T390	0	372	0	0
T391	0	2711	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	239	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	7	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	1	0	0
T368	0	12	0	0
T380	0	2	0	0
T382	0	4	0	0
T390	0	1	0	0
T391	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T393

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T74,T138
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	101907	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	258	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	101907	0	0
T2	484077	405	0	0
T3	130393	0	0	0
T74	0	627	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	840	0	0
T139	0	1925	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2878	0	0
T368	0	3168	0	0
T380	0	697	0	0
T382	0	7598	0	0
T390	0	432	0	0
T391	0	3895	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	258	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	5	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	7	0	0
T368	0	8	0	0
T380	0	2	0	0
T382	0	18	0	0
T390	0	1	0	0
T391	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	94890	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	239	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	94890	0	0
T1	31246	269	0	0
T2	0	459	0	0
T5	17214	0	0	0
T11	0	392	0	0
T12	0	292	0	0
T15	363682	0	0	0
T38	57571	0	0	0
T59	45088	0	0	0
T74	0	620	0	0
T86	19073	0	0	0
T87	303595	0	0	0
T88	39814	0	0	0
T89	54816	0	0	0
T102	116201	0	0	0
T138	0	886	0	0
T139	0	735	0	0
T367	0	3776	0	0
T368	0	6085	0	0
T390	0	410	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	239	0	0
T1	31246	1	0	0
T2	0	1	0	0
T5	17214	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	363682	0	0	0
T38	57571	0	0	0
T59	45088	0	0	0
T74	0	2	0	0
T86	19073	0	0	0
T87	303595	0	0	0
T88	39814	0	0	0
T89	54816	0	0	0
T102	116201	0	0	0
T138	0	2	0	0
T139	0	2	0	0
T367	0	9	0	0
T368	0	15	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T13,T74

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T13,T74
1	1	Covered	T2,T13,T74

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T13,T74

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T74
1	1	Covered	T2,T13,T74

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T13,T74
0	0	1	Covered	T2,T13,T74
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T13,T74
0	0	1	Covered	T2,T13,T74
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	110637	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	279	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	110637	0	0
T2	484077	482	0	0
T3	130393	0	0	0
T13	0	268	0	0
T74	0	512	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	798	0	0
T139	0	3533	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2480	0	0
T368	0	3700	0	0
T380	0	802	0	0
T390	0	377	0	0
T391	0	1947	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	279	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T13	0	1	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	9	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	6	0	0
T368	0	9	0	0
T380	0	2	0	0
T390	0	1	0	0
T391	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	96728	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	243	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	96728	0	0
T2	484077	445	0	0
T3	130393	0	0	0
T74	0	631	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	865	0	0
T139	0	430	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	3692	0	0
T368	0	3555	0	0
T380	0	668	0	0
T382	0	3790	0	0
T390	0	409	0	0
T391	0	1164	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	243	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	1	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	9	0	0
T368	0	9	0	0
T380	0	2	0	0
T382	0	9	0	0
T390	0	1	0	0
T391	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	104295	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	264	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	104295	0	0
T2	484077	455	0	0
T3	130393	0	0	0
T74	0	631	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	746	0	0
T139	0	3100	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	1526	0	0
T368	0	6398	0	0
T380	0	677	0	0
T382	0	6655	0	0
T390	0	434	0	0
T391	0	3492	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	264	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	8	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	4	0	0
T368	0	16	0	0
T380	0	2	0	0
T382	0	16	0	0
T390	0	1	0	0
T391	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	108654	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	271	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	108654	0	0
T2	484077	434	0	0
T3	130393	0	0	0
T74	0	672	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	789	0	0
T139	0	371	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	819	0	0
T368	0	7851	0	0
T380	0	763	0	0
T382	0	5220	0	0
T390	0	406	0	0
T391	0	3180	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	271	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	1	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2	0	0
T368	0	20	0	0
T380	0	2	0	0
T382	0	12	0	0
T390	0	1	0	0
T391	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T3,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T3,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	102662	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	262	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	102662	0	0
T2	484077	458	0	0
T3	130393	540	0	0
T8	0	364	0	0
T9	0	799	0	0
T10	0	387	0	0
T57	0	379	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T99	0	273	0	0
T100	0	245	0	0
T101	0	247	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T392	0	403	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	262	0	0
T2	484077	1	0	0
T3	130393	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T57	0	1	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T392	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T393

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	115136	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	289	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	115136	0	0
T2	484077	376	0	0
T3	130393	0	0	0
T74	0	562	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	902	0	0
T139	0	2360	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	3235	0	0
T368	0	6458	0	0
T380	0	752	0	0
T382	0	4691	0	0
T390	0	449	0	0
T391	0	1090	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	289	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	6	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	8	0	0
T368	0	16	0	0
T380	0	2	0	0
T382	0	11	0	0
T390	0	1	0	0
T391	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T393

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	100599	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	254	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	100599	0	0
T2	484077	482	0	0
T3	130393	0	0	0
T74	0	565	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	825	0	0
T139	0	2729	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2002	0	0
T368	0	3916	0	0
T380	0	758	0	0
T382	0	7632	0	0
T390	0	439	0	0
T391	0	1134	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	254	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	7	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	5	0	0
T368	0	10	0	0
T380	0	2	0	0
T382	0	18	0	0
T390	0	1	0	0
T391	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T74,T138
1	1	Covered	T2,T74,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T74,T138
0	0	1	Covered	T2,T74,T138
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	92775	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	234	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	92775	0	0
T2	484077	403	0	0
T3	130393	0	0	0
T74	0	674	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	866	0	0
T139	0	4027	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	1999	0	0
T368	0	3593	0	0
T380	0	702	0	0
T382	0	3023	0	0
T390	0	454	0	0
T391	0	345	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	234	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	10	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	5	0	0
T368	0	9	0	0
T380	0	2	0	0
T382	0	7	0	0
T390	0	1	0	0
T391	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	138486770	110096	0	0
DstReqKnown_A	1721347	1511025	0	0
SrcAckBusyChk_A	138486770	276	0	0
SrcBusyKnown_A	138486770	137724169	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	110096	0	0
T2	484077	458	0	0
T3	130393	0	0	0
T6	0	289	0	0
T7	0	365	0	0
T14	0	406	0	0
T74	0	696	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	855	0	0
T139	0	2826	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	2478	0	0
T368	0	5952	0	0
T390	0	468	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721347	1511025	0	0
T1	483	311	0	0
T4	720	547	0	0
T5	467	296	0	0
T15	6578	6090	0	0
T38	757	584	0	0
T59	933	759	0	0
T86	336	164	0	0
T87	2647	2582	0	0
T88	546	372	0	0
T89	812	638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	276	0	0
T2	484077	1	0	0
T3	130393	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T14	0	1	0	0
T74	0	2	0	0
T97	342612	0	0	0
T98	35417	0	0	0
T138	0	2	0	0
T139	0	7	0	0
T273	18583	0	0	0
T274	23228	0	0	0
T275	42993	0	0	0
T276	80396	0	0	0
T277	58418	0	0	0
T332	39581	0	0	0
T367	0	6	0	0
T368	0	15	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138486770	137724169	0	0
T1	31246	30561	0	0
T4	52075	51758	0	0
T5	17214	16947	0	0
T15	363682	362229	0	0
T38	57571	56886	0	0
T59	45088	44482	0	0
T86	19073	18293	0	0
T87	303595	303073	0	0
T88	39814	39084	0	0
T89	54816	54395	0	0