Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	153945	1			T74	72		T76	12		T78	3
values[2]	3817	1			T74	2		T502	1		T514	1
values[3]	1972	1			T502	1		T504	1		T416	1
values[4]	1549	1			T502	1		T416	1		T525	29
values[5]	1160	1			T502	1		T416	1		T525	21
values[6]	967	1			T502	1		T416	1		T525	7
values[7]	881	1			T502	1		T416	1		T525	5
values[8]	793	1			T502	1		T416	1		T525	3
values[9]	675	1			T502	1		T416	1		T525	12
values[10]	649	1			T502	1		T416	1		T525	4
values[11]	566	1			T502	1		T416	1		T525	5
values[12]	495	1			T502	1		T416	1		T525	23
values[13]	447	1			T502	1		T416	1		T525	11
values[14]	494	1			T502	1		T416	1		T525	19
values[15]	557	1			T502	1		T416	1		T525	25
values[16]	485	1			T502	1		T416	1		T525	10
values[17]	348	1			T502	1		T416	1		T525	9
values[18]	285	1			T502	1		T416	1		T525	10
values[19]	275	1			T502	1		T416	1		T525	7
values[20]	285	1			T502	1		T416	1		T525	2
values[21]	278	1			T502	1		T416	1		T525	2
values[22]	305	1			T502	1		T416	1		T525	26
values[23]	299	1			T502	1		T416	1		T525	13
values[24]	246	1			T502	1		T416	1		T525	11
values[25]	261	1			T502	1		T416	1		T525	21
values[26]	247	1			T502	1		T416	1		T525	19
values[27]	179	1			T502	1		T416	1		T525	5
values[28]	217	1			T502	1		T416	1		T802	1
values[29]	241	1			T502	1		T416	1		T802	1
values[30]	197	1			T502	1		T416	1		T802	1
values[31]	184	1			T502	1		T416	1		T802	2
values[32]	158	1			T502	1		T416	1		T802	1
values[33]	129	1			T502	1		T416	1		T802	1
values[34]	112	1			T502	1		T416	1		T802	1
values[35]	102	1			T502	1		T416	1		T802	1
values[36]	89	1			T502	1		T416	1		T802	1
values[37]	77	1			T502	1		T416	1		T802	1
values[38]	66	1			T502	1		T416	1		T802	1
values[39]	66	1			T502	1		T416	1		T802	1
values[40]	64	1			T502	1		T416	1		T802	1
values[41]	69	1			T502	1		T416	1		T802	1
values[42]	76	1			T502	1		T416	1		T802	1
values[43]	65	1			T502	1		T416	1		T802	1
values[44]	64	1			T502	1		T416	1		T802	1
values[45]	59	1			T502	1		T416	1		T802	1
values[46]	83	1			T502	1		T416	1		T802	1
values[47]	84	1			T502	1		T416	1		T802	1
values[48]	56	1			T502	1		T416	1		T802	1
values[49]	56	1			T502	1		T416	1		T802	1
values[50]	62	1			T502	1		T416	1		T802	1
values[51]	67	1			T502	1		T416	1		T802	1
values[52]	63	1			T502	1		T416	1		T802	1
values[53]	68	1			T502	1		T416	1		T802	1
values[54]	57	1			T502	1		T416	1		T802	1
values[55]	58	1			T502	1		T416	1		T802	1
values[56]	64	1			T502	1		T416	1		T802	1
values[57]	72	1			T502	1		T416	1		T802	1
values[58]	64	1			T502	1		T416	1		T802	1
values[59]	77	1			T502	1		T416	1		T802	1
values[60]	86	1			T502	1		T416	1		T802	1
values[61]	60	1			T502	1		T416	1		T802	1
values[62]	74	1			T502	1		T416	1		T802	1
values[63]	66	1			T502	1		T416	1		T802	1
values[64]	60	1			T502	1		T416	1		T802	1
values[65]	59	1			T502	1		T416	1		T802	1
values[66]	70	1			T502	1		T416	1		T802	1
values[67]	78	1			T502	1		T416	1		T802	1
values[68]	70	1			T502	1		T416	1		T802	1
values[69]	85	1			T502	1		T416	1		T802	1
values[70]	54	1			T502	1		T416	1		T802	1
values[71]	54	1			T502	1		T416	1		T802	1
values[72]	60	1			T502	1		T416	1		T802	1
values[73]	79	1			T502	1		T416	1		T802	1
values[74]	60	1			T502	1		T416	1		T802	1
values[75]	69	1			T502	1		T416	1		T802	1
values[76]	65	1			T502	1		T416	1		T802	1
values[77]	82	1			T502	3		T416	1		T802	1
values[78]	77	1			T502	7		T416	1		T802	1
values[79]	71	1			T502	3		T416	1		T802	1
values[80]	78	1			T502	6		T416	1		T802	1
values[81]	80	1			T502	5		T416	1		T802	1
values[82]	98	1			T502	5		T416	1		T802	2
values[83]	82	1			T502	4		T416	1		T802	1
values[84]	84	1			T502	2		T416	1		T802	1
values[85]	82	1			T502	1		T416	1		T802	1
values[86]	103	1			T502	1		T416	1		T802	1
values[87]	102	1			T502	3		T416	1		T802	1
values[88]	83	1			T502	4		T416	1		T802	1
values[89]	87	1			T502	7		T416	1		T802	1
values[90]	80	1			T502	4		T416	1		T802	1
values[91]	98	1			T502	3		T416	1		T802	1
values[92]	102	1			T502	5		T416	1		T802	1
values[93]	108	1			T502	1		T416	1		T802	1
values[94]	83	1			T502	1		T416	1		T802	1
values[95]	103	1			T502	1		T416	1		T802	1
values[96]	80	1			T502	1		T416	1		T802	1
values[97]	103	1			T502	2		T416	1		T802	1
values[98]	111	1			T502	1		T416	1		T802	1
values[99]	93	1			T502	2		T416	1		T802	1
values[100]	103	1			T502	2		T416	1		T802	1
values[101]	94	1			T502	2		T416	1		T802	1
values[102]	99	1			T502	2		T416	1		T802	1
values[103]	91	1			T502	5		T416	1		T802	1
values[104]	103	1			T502	2		T416	1		T802	1
values[105]	112	1			T502	5		T416	1		T802	1
values[106]	93	1			T502	2		T416	1		T802	1
values[107]	96	1			T502	2		T416	1		T802	1
values[108]	113	1			T502	4		T416	1		T802	1
values[109]	100	1			T502	2		T416	1		T802	1
values[110]	101	1			T502	2		T416	1		T802	1
values[111]	92	1			T502	1		T416	1		T802	1
values[112]	91	1			T502	2		T416	1		T802	1
values[113]	107	1			T502	2		T416	1		T802	1
values[114]	131	1			T502	1		T416	1		T802	1
values[115]	116	1			T502	2		T416	1		T802	1
values[116]	116	1			T502	1		T416	2		T802	1
values[117]	113	1			T502	1		T416	1		T802	1
values[118]	118	1			T502	2		T416	1		T802	1
values[119]	119	1			T502	1		T416	3		T802	3
values[120]	119	1			T502	1		T416	2		T802	2
values[121]	134	1			T502	2		T416	3		T802	2
values[122]	126	1			T502	3		T416	2		T802	4
values[123]	177	1			T502	6		T416	1		T802	2
values[124]	238	1			T502	1		T416	1		T802	2
values[125]	412	1			T502	1		T416	2		T802	1
values[126]	871	1			T502	14		T416	7		T802	26
values[127]	2603	1			T502	102		T416	113		T802	147
values[128]	4443	1			T502	155		T416	273		T802	262