Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.46	93.71	95.36		94.43	97.53	99.57

Total tests in report: 2870

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.23	39.23	45.00	45.00	43.33	43.33	26.02	26.02			58.07	58.07	62.76	62.76	0.18	0.18	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3395039328
48.49	9.26	50.37	5.38	58.97	15.64	26.45	0.43			68.24	10.17	85.84	23.08	1.07	0.89	/workspace/coverage/cover_reg_top/2.chip_csr_rw.2298348126
56.75	8.26	61.56	11.19	61.23	2.26	29.39	2.95			69.04	0.80	85.84	0.00	33.45	32.38	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.36185280
62.39	5.64	74.05	12.49	69.18	7.95	31.70	2.30			80.14	11.10	85.84	0.00	33.45	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3852208299
66.29	3.90	74.05	0.00	70.16	0.98	31.70	0.00			80.34	0.20	85.84	0.00	55.68	22.23	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1840215128
69.78	3.48	80.10	6.05	74.53	4.37	35.62	3.92			82.36	2.02	90.38	4.55	55.68	0.00	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2898104716
73.25	3.47	80.10	0.01	74.55	0.02	56.04	20.42			82.38	0.02	90.73	0.35	55.69	0.01	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2717304768
75.48	2.23	82.15	2.05	74.88	0.33	61.98	5.93			82.64	0.26	90.73	0.00	60.50	4.81	/workspace/coverage/cover_reg_top/40.xbar_error_random.1147980431
77.46	1.98	84.42	2.27	77.60	2.72	66.60	4.62			84.54	1.91	91.08	0.35	60.50	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_rma.4064174540
79.23	1.77	84.42	0.00	77.60	0.00	66.60	0.00			84.54	0.00	91.08	0.00	71.11	10.61	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.4193900687
80.69	1.47	84.71	0.29	77.75	0.15	74.44	7.84			84.72	0.18	91.43	0.35	71.11	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.394551112
82.05	1.36	86.85	2.14	79.69	1.94	76.19	1.75			87.03	2.31	91.43	0.00	71.11	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3672091290
83.27	1.22	88.72	1.86	82.42	2.73	76.45	0.26			89.51	2.47	91.43	0.00	71.11	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2128805582
84.43	1.16	88.72	0.00	82.57	0.15	76.45	0.00			89.56	0.05	91.43	0.00	77.85	6.74	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.58179392
85.47	1.04	89.33	0.61	83.36	0.79	78.42	1.97			90.09	0.53	91.43	0.00	80.17	2.31	/workspace/coverage/default/0.chip_sw_alert_test.1069972250
86.45	0.98	89.33	0.00	83.36	0.00	78.42	0.00			90.09	0.00	91.43	0.00	86.05	5.89	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2480944176
87.29	0.84	90.08	0.76	83.56	0.20	78.43	0.01			90.34	0.25	95.28	3.85	86.05	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.951532670
88.08	0.79	90.55	0.46	83.64	0.08	82.59	4.16			90.34	0.01	95.28	0.00	86.05	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.1814235860
88.75	0.67	90.55	0.00	84.15	0.51	82.62	0.03			90.46	0.11	95.28	0.00	89.44	3.38	/workspace/coverage/cover_reg_top/95.xbar_stress_all.2922669822
89.30	0.55	90.55	0.00	84.15	0.00	82.62	0.00			90.46	0.00	95.28	0.00	92.75	3.31	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1359798619
89.78	0.48	90.55	0.00	84.15	0.00	82.62	0.00			90.46	0.00	95.28	0.00	95.65	2.90	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2797824182
90.26	0.47	91.28	0.73	85.06	0.91	83.06	0.44			91.22	0.76	95.28	0.00	95.65	0.00	/workspace/coverage/default/2.chip_sw_gpio.152485951
90.72	0.46	91.90	0.62	85.71	0.65	83.82	0.76			91.95	0.73	95.28	0.00	95.65	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.510824806
91.14	0.42	91.91	0.01	87.78	2.07	83.82	0.00			91.95	0.00	95.28	0.00	96.08	0.42	/workspace/coverage/cover_reg_top/7.chip_tl_errors.2184965220
91.55	0.41	92.02	0.11	87.90	0.12	85.76	1.94			92.04	0.09	95.28	0.00	96.28	0.20	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2590518764
91.86	0.31	92.52	0.50	88.60	0.70	86.07	0.31			92.41	0.37	95.28	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1224641714
92.15	0.29	92.52	0.00	88.62	0.02	87.77	1.70			92.41	0.00	95.28	0.00	96.28	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.397324799
92.40	0.25	92.61	0.09	88.65	0.02	88.44	0.68			92.41	0.00	95.98	0.70	96.29	0.01	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1121196570
92.58	0.18	92.61	0.00	88.65	0.00	89.54	1.10			92.41	0.00	95.98	0.00	96.29	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.4006584528
92.74	0.16	92.61	0.00	88.73	0.08	89.54	0.00			92.41	0.00	95.98	0.00	97.19	0.90	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4014672957
92.90	0.16	92.83	0.22	88.90	0.17	89.81	0.27			92.54	0.12	96.15	0.17	97.19	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1979469076
93.06	0.15	92.83	0.00	88.90	0.00	90.74	0.93			92.54	0.00	96.15	0.00	97.19	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1496608883
93.20	0.15	93.10	0.27	89.15	0.26	90.77	0.03			92.85	0.32	96.15	0.00	97.19	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3667464992
93.34	0.14	93.11	0.01	89.53	0.38	90.80	0.03			93.27	0.42	96.15	0.00	97.19	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4112226994
93.48	0.14	93.27	0.16	89.64	0.11	90.90	0.09			93.40	0.12	96.50	0.35	97.19	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1613201096
93.61	0.12	93.59	0.32	89.90	0.25	91.06	0.16			93.40	0.00	96.50	0.00	97.19	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3403111184
93.73	0.12	93.60	0.01	89.90	0.00	91.73	0.67			93.40	0.00	96.50	0.00	97.23	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3723409098
93.83	0.11	93.76	0.16	90.23	0.33	91.74	0.01			93.53	0.14	96.50	0.00	97.23	0.00	/workspace/coverage/cover_reg_top/17.chip_csr_rw.852894654
93.94	0.11	93.76	0.00	90.23	0.01	91.74	0.00			93.53	0.00	96.50	0.00	97.86	0.63	/workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3528140956
94.04	0.11	94.02	0.26	90.34	0.11	91.93	0.19			93.60	0.06	96.50	0.00	97.87	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4204901962
94.15	0.10	94.08	0.06	90.38	0.04	92.40	0.47			93.63	0.03	96.50	0.00	97.87	0.00	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2314063180
94.25	0.10	94.08	0.00	90.98	0.60	92.40	0.00			93.63	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.2816013414
94.34	0.10	94.08	0.00	90.98	0.00	92.99	0.59			93.63	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3481052657
94.42	0.08	94.10	0.03	91.01	0.02	93.23	0.24			93.66	0.02	96.68	0.17	97.87	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3451973197
94.50	0.07	94.12	0.01	91.20	0.19	93.25	0.02			93.87	0.21	96.68	0.00	97.87	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3578356287
94.56	0.06	94.23	0.11	91.30	0.10	93.33	0.08			93.95	0.08	96.68	0.00	97.87	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.758824424
94.62	0.06	94.24	0.01	91.30	0.01	93.70	0.37			93.95	0.00	96.68	0.00	97.87	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.722674957
94.68	0.06	94.24	0.00	91.41	0.11	93.70	0.00			93.95	0.00	96.68	0.00	98.13	0.26	/workspace/coverage/cover_reg_top/3.xbar_stress_all.1172633297
94.74	0.05	94.25	0.01	91.41	0.01	93.82	0.13			93.96	0.01	96.85	0.17	98.13	0.00	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2191495998
94.78	0.05	94.30	0.05	91.48	0.07	93.94	0.11			94.00	0.05	96.85	0.00	98.13	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1632582381
94.83	0.04	94.37	0.07	91.61	0.12	93.94	0.00			94.07	0.06	96.85	0.00	98.13	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.4126514430
94.87	0.04	94.38	0.01	91.62	0.01	93.94	0.00			94.09	0.02	97.03	0.17	98.14	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2312746452
94.90	0.04	94.41	0.04	91.79	0.17	93.94	0.01			94.11	0.02	97.03	0.00	98.14	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2886936390
94.94	0.04	94.41	0.00	92.02	0.23	93.94	0.00			94.11	0.00	97.03	0.00	98.14	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.4227826144
94.98	0.04	94.41	0.00	92.24	0.23	93.94	0.00			94.11	0.00	97.03	0.00	98.14	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.534670613
95.02	0.04	94.42	0.01	92.26	0.01	93.95	0.01			94.12	0.01	97.20	0.17	98.16	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1347938028
95.05	0.04	94.42	0.01	92.27	0.01	93.96	0.01			94.13	0.01	97.38	0.17	98.17	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.636233418
95.09	0.04	94.43	0.01	92.28	0.01	93.96	0.00			94.13	0.01	97.55	0.17	98.18	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4224995007
95.12	0.03	94.46	0.03	92.37	0.08	94.01	0.05			94.17	0.03	97.55	0.00	98.18	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2073263175
95.15	0.03	94.49	0.03	92.42	0.05	94.08	0.07			94.19	0.02	97.55	0.00	98.18	0.00	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2315870683
95.18	0.03	94.49	0.00	92.42	0.01	94.08	0.00			94.19	0.00	97.55	0.00	98.34	0.16	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2029979362
95.21	0.03	94.56	0.07	92.42	0.00	94.17	0.09			94.20	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2264646432
95.24	0.03	94.56	0.00	92.42	0.00	94.34	0.17			94.20	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.189680346
95.26	0.03	94.56	0.00	92.53	0.11	94.34	0.00			94.22	0.02	97.55	0.00	98.38	0.04	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2859008592
95.29	0.03	94.63	0.07	92.60	0.07	94.34	0.00			94.24	0.02	97.55	0.00	98.38	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4276358786
95.31	0.02	94.69	0.07	92.65	0.05	94.34	0.00			94.27	0.03	97.55	0.00	98.38	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1316192629
95.34	0.02	94.69	0.00	92.65	0.00	94.48	0.14			94.27	0.00	97.55	0.00	98.38	0.00	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.414526560
95.36	0.02	94.69	0.00	92.68	0.03	94.48	0.00			94.27	0.00	97.55	0.00	98.47	0.09	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2215314817
95.38	0.02	94.69	0.00	92.68	0.00	94.60	0.12			94.27	0.00	97.55	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1359711539
95.40	0.02	94.72	0.03	92.72	0.04	94.61	0.01			94.30	0.02	97.55	0.00	98.47	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.614878599
95.41	0.02	94.72	0.00	92.79	0.07	94.61	0.00			94.33	0.03	97.55	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all.3232826365
95.43	0.02	94.73	0.01	92.81	0.01	94.68	0.07			94.34	0.01	97.55	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_usbdev_dpi.82208729
95.45	0.02	94.73	0.00	92.91	0.10	94.68	0.00			94.34	0.00	97.55	0.00	98.47	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2211627141
95.46	0.02	94.73	0.00	92.99	0.08	94.68	0.00			94.34	0.00	97.55	0.00	98.48	0.01	/workspace/coverage/cover_reg_top/28.chip_tl_errors.1953696425
95.48	0.01	94.73	0.00	93.00	0.01	94.68	0.00			94.34	0.00	97.55	0.00	98.57	0.08	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.931063535
95.49	0.01	94.73	0.00	93.04	0.05	94.68	0.00			94.34	0.00	97.55	0.00	98.60	0.04	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.157714929
95.50	0.01	94.73	0.01	93.06	0.02	94.74	0.05			94.34	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4153104872
95.52	0.01	94.73	0.00	93.06	0.00	94.81	0.07			94.34	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2933574389
95.53	0.01	94.74	0.01	93.06	0.00	94.87	0.06			94.34	0.00	97.55	0.00	98.61	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2720382613
95.54	0.01	94.74	0.00	93.07	0.01	94.87	0.00			94.34	0.00	97.55	0.00	98.67	0.06	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3668569778
95.55	0.01	94.75	0.01	93.10	0.03	94.87	0.00			94.36	0.02	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3832199717
95.56	0.01	94.75	0.00	93.10	0.00	94.93	0.06			94.36	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3479115922
95.57	0.01	94.75	0.00	93.16	0.06	94.93	0.00			94.36	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2008179410
95.58	0.01	94.75	0.00	93.22	0.06	94.93	0.00			94.36	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1210817203
95.59	0.01	94.75	0.00	93.24	0.02	94.93	0.00			94.36	0.00	97.55	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.29447252
95.60	0.01	94.75	0.00	93.25	0.01	94.96	0.03			94.37	0.01	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2748044978
95.61	0.01	94.77	0.02	93.26	0.01	94.96	0.01			94.39	0.02	97.55	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3983661726
95.61	0.01	94.77	0.00	93.30	0.04	94.96	0.00			94.39	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.3922296544
95.62	0.01	94.77	0.00	93.30	0.00	95.00	0.04			94.39	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3914098219
95.63	0.01	94.78	0.01	93.32	0.02	95.01	0.01			94.39	0.01	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2889140985
95.63	0.01	94.80	0.02	93.33	0.01	95.01	0.00			94.41	0.02	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3586775230
95.64	0.01	94.80	0.00	93.37	0.04	95.01	0.00			94.41	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.916541481
95.65	0.01	94.82	0.02	93.37	0.01	95.02	0.01			94.41	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.659335273
95.65	0.01	94.82	0.00	93.37	0.00	95.06	0.04			94.41	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2271393147
95.66	0.01	94.82	0.00	93.39	0.01	95.06	0.00			94.41	0.00	97.55	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.557736051
95.66	0.01	94.82	0.00	93.39	0.00	95.09	0.03			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1784971015
95.67	0.01	94.83	0.01	93.40	0.01	95.10	0.01			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2799322645
95.67	0.01	94.83	0.00	93.41	0.01	95.11	0.02			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1378836551
95.68	0.01	94.83	0.00	93.43	0.03	95.11	0.00			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1143638164
95.68	0.01	94.83	0.00	93.44	0.01	95.14	0.02			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2484941057
95.69	0.01	94.83	0.00	93.44	0.00	95.16	0.03			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3440647807
95.69	0.01	94.83	0.00	93.44	0.00	95.19	0.03			94.41	0.00	97.55	0.00	98.73	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2168328736
95.70	0.01	94.83	0.00	93.45	0.01	95.19	0.00			94.41	0.00	97.55	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.703217850
95.70	0.01	94.85	0.02	93.45	0.00	95.19	0.01			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.2967176483
95.71	0.01	94.85	0.00	93.45	0.01	95.21	0.02			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.502477355
95.71	0.01	94.85	0.00	93.47	0.02	95.21	0.00			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/80.xbar_access_same_device.3110106941
95.71	0.01	94.85	0.00	93.49	0.02	95.22	0.01			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3178020412
95.72	0.01	94.85	0.00	93.49	0.00	95.23	0.02			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3232662909
95.72	0.01	94.85	0.00	93.51	0.02	95.23	0.00			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2605050818
95.72	0.01	94.85	0.00	93.52	0.02	95.23	0.00			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1336807951
95.72	0.01	94.85	0.00	93.54	0.02	95.23	0.00			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_gpio.2134039091
95.73	0.01	94.85	0.00	93.56	0.02	95.23	0.00			94.41	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.588635259
95.73	0.01	94.85	0.00	93.56	0.00	95.24	0.01			94.41	0.00	97.55	0.00	98.77	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.189288897
95.73	0.01	94.85	0.00	93.57	0.01	95.24	0.00			94.41	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3880566044
95.73	0.01	94.85	0.00	93.59	0.01	95.24	0.00			94.41	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.534930720
95.74	0.01	94.85	0.00	93.59	0.00	95.24	0.01			94.41	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.20183654
95.74	0.01	94.85	0.00	93.59	0.00	95.25	0.01			94.41	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3980809873
95.74	0.01	94.85	0.00	93.59	0.00	95.27	0.01			94.41	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.217171303
95.74	0.01	94.86	0.01	93.59	0.01	95.27	0.00			94.41	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.3773445136
95.75	0.01	94.88	0.01	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.2643067756
95.75	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1886865698
95.75	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2389721826
95.75	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2953592737
95.75	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829124065
95.76	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2593418617
95.76	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2590765422
95.76	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3781178565
95.76	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716415733
95.76	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1781751858
95.77	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1217168083
95.77	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.371017493
95.77	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.566949240
95.77	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3578075370
95.77	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3829454149
95.78	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.302229825
95.78	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3865188739
95.78	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2208691106
95.78	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342382850
95.78	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1748957172
95.79	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.240105644
95.79	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2477170511
95.79	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2467578085
95.79	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.970743047
95.79	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.247087648
95.80	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634806246
95.80	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.678855910
95.80	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1907489513
95.80	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.461955222
95.80	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.660768376
95.81	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1102402728
95.81	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1531382193
95.81	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1790151951
95.81	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2649848360
95.81	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.4157346738
95.81	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.56413009
95.82	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2145051830
95.82	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.588700798
95.82	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2702757536
95.82	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1650798842
95.82	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2091131642
95.83	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2205342798
95.83	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.226741133
95.83	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4254369398
95.83	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1942811097
95.83	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.31	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3679555103
95.84	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2167343736
95.84	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.33	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1871895359
95.84	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.34	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2484194779
95.84	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.35	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1967219603
95.84	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.37	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2335237278
95.85	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.38	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3125171675
95.85	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.39	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.2531955449
95.85	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.40	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.340274551
95.85	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.41	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.827330590
95.85	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.42	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1980330231
95.86	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.44	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1443060392
95.86	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.117201940
95.86	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1556050842
95.86	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/60.chip_sw_all_escalation_resets.258158969
95.86	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3392965756
95.87	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.45734313
95.87	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2937080589
95.87	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655179645
95.87	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3126992937
95.87	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.4032107672
95.88	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3434347566
95.88	0.01	94.88	0.00	93.59	0.00	95.27	0.00			94.41	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.1726722457
95.88	0.01	94.88	0.00	93.60	0.01	95.27	0.00			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_gpio.2221006342
95.88	0.01	94.88	0.00	93.61	0.01	95.27	0.00			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2316188950
95.88	0.01	94.88	0.00	93.63	0.01	95.27	0.00			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.317957455
95.88	0.01	94.88	0.00	93.63	0.00	95.28	0.01			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3806087883
95.89	0.01	94.88	0.00	93.63	0.00	95.29	0.01			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.889832854
95.89	0.01	94.88	0.00	93.63	0.00	95.30	0.01			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1653988588
95.89	0.01	94.88	0.00	93.63	0.00	95.31	0.01			94.41	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.540606477
95.89	0.01	94.88	0.00	93.63	0.00	95.31	0.00			94.42	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.292637579
95.89	0.01	94.88	0.00	93.63	0.00	95.31	0.00			94.43	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.360104286
95.89	0.01	94.88	0.00	93.63	0.01	95.31	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1733559779
95.89	0.01	94.88	0.00	93.64	0.01	95.31	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.578656487
95.90	0.01	94.88	0.00	93.65	0.01	95.31	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1948002981
95.90	0.01	94.88	0.00	93.65	0.01	95.31	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3388951098
95.90	0.01	94.88	0.00	93.66	0.01	95.31	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3307574417
95.90	0.01	94.88	0.00	93.66	0.00	95.31	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2278238081
95.90	0.01	94.88	0.00	93.66	0.00	95.32	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1914869371
95.90	0.01	94.88	0.00	93.66	0.01	95.32	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2046648440
95.90	0.01	94.88	0.00	93.66	0.00	95.33	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.4105373939
95.90	0.01	94.88	0.00	93.66	0.00	95.33	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1862438702
95.90	0.01	94.88	0.00	93.66	0.00	95.34	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.711020015
95.90	0.01	94.88	0.00	93.67	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2381022439
95.90	0.01	94.88	0.00	93.67	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.550904746
95.91	0.01	94.88	0.00	93.67	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.106937096
95.91	0.01	94.88	0.00	93.68	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.179280682
95.91	0.01	94.88	0.00	93.68	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1212438768
95.91	0.01	94.88	0.00	93.69	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.429124986
95.91	0.01	94.88	0.00	93.69	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1395821351
95.91	0.01	94.88	0.00	93.69	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3132061954
95.91	0.01	94.88	0.00	93.70	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.44345823
95.91	0.01	94.88	0.00	93.70	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.209815019
95.91	0.01	94.88	0.00	93.70	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3530306674
95.91	0.01	94.88	0.00	93.71	0.01	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2571555689
95.91	0.01	94.88	0.00	93.71	0.00	95.34	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1262514835
95.91	0.01	94.88	0.01	93.71	0.00	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2363449550
95.91	0.01	94.88	0.01	93.71	0.00	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2953137786
95.91	0.01	94.89	0.01	93.71	0.00	95.34	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.441983881
95.91	0.01	94.89	0.00	93.71	0.00	95.34	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.778375683
95.91	0.01	94.89	0.00	93.71	0.00	95.34	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2098087202
95.91	0.01	94.89	0.00	93.71	0.00	95.35	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3324636564
95.91	0.01	94.89	0.00	93.71	0.00	95.35	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.91281015
95.91	0.01	94.89	0.00	93.71	0.00	95.35	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.966864009
95.92	0.01	94.89	0.00	93.71	0.00	95.35	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1380980097
95.92	0.01	94.89	0.00	93.71	0.00	95.36	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2315358487

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3135715197
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.751038807
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3897252075
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3837318528
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2287252671
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.19645662
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1340566460
/workspace/coverage/cover_reg_top/0.chip_tl_errors.426689412
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1154633557
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1113438774
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.720931564
/workspace/coverage/cover_reg_top/0.xbar_error_random.2313659704
/workspace/coverage/cover_reg_top/0.xbar_random.3956720974
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.841550602
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.202854447
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3423732166
/workspace/coverage/cover_reg_top/0.xbar_same_source.3460614599
/workspace/coverage/cover_reg_top/0.xbar_smoke.2550142660
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1094920677
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.512728421
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1671726870
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2757095764
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.322941189
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.172651376
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2788565658
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2481342819
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2697277287
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1976186752
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1645878075
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.694279262
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1205074633
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4088000214
/workspace/coverage/cover_reg_top/1.chip_tl_errors.4196214371
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2532773240
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.958714641
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.457336005
/workspace/coverage/cover_reg_top/1.xbar_error_random.3008001789
/workspace/coverage/cover_reg_top/1.xbar_random.552405388
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2310737695
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.267727101
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1189958949
/workspace/coverage/cover_reg_top/1.xbar_same_source.1973983291
/workspace/coverage/cover_reg_top/1.xbar_smoke.2207791407
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.630811138
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.446732481
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2833700056
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2625543033
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.520431956
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3406468451
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3691280272
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1602364691
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1170881947
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2398996974
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.15438966
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2627673577
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1734685771
/workspace/coverage/cover_reg_top/10.xbar_error_random.1094177806
/workspace/coverage/cover_reg_top/10.xbar_random.34929608
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.107744021
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3187236476
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.387368602
/workspace/coverage/cover_reg_top/10.xbar_same_source.3068405121
/workspace/coverage/cover_reg_top/10.xbar_smoke.1809295590
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1311737944
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.381348664
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3395739
/workspace/coverage/cover_reg_top/10.xbar_stress_all.607617235
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.372187767
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2025593662
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.218329419
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2606331544
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1782911661
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.308040779
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3409398172
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.818742822
/workspace/coverage/cover_reg_top/11.xbar_error_random.2662172276
/workspace/coverage/cover_reg_top/11.xbar_random.4110518928
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3786293737
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3670272652
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.171254813
/workspace/coverage/cover_reg_top/11.xbar_same_source.3283203802
/workspace/coverage/cover_reg_top/11.xbar_smoke.2428851547
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2548057597
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2973249876
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2386146964
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1878255657
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2550324162
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1206879189
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3757167873
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.384707372
/workspace/coverage/cover_reg_top/12.chip_csr_rw.445888506
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3409879199
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1726123676
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.713244379
/workspace/coverage/cover_reg_top/12.xbar_error_random.3980918677
/workspace/coverage/cover_reg_top/12.xbar_random.2901479460
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.678762608
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.53764914
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3699633320
/workspace/coverage/cover_reg_top/12.xbar_same_source.1811264179
/workspace/coverage/cover_reg_top/12.xbar_smoke.2970021757
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3398148013
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3251912191
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1381415327
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1630617789
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3868018101
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2516753380
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2771538187
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2917565449
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1617523896
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1318563183
/workspace/coverage/cover_reg_top/13.chip_tl_errors.847334204
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3668050153
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.4073290097
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.259424075
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/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2727131868
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1781656436
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/workspace/coverage/default/20.chip_sw_all_escalation_resets.3575925472
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/workspace/coverage/default/27.chip_sw_all_escalation_resets.4242369327
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/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3080942015
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2739745490
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3002628548
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2588497088
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2017841534
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2289142849
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.917932465
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2813016145
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.40705798
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1333124146
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3239929668
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3908744022
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3386869587
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3105810831
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.554616849
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2714139004
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1909007457
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2524850519
/workspace/coverage/default/4.chip_tap_straps_dev.2802892839
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/workspace/coverage/default/4.chip_tap_straps_rma.1231268269
/workspace/coverage/default/4.chip_tap_straps_testunlock0.507035823
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1847553613
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2042002591
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3121790930
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301274644
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3911777446
/workspace/coverage/default/44.chip_sw_all_escalation_resets.303865159
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319455965
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2078139522
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2619756635
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1974584136
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.190474188
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1835462466
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3725323030
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3178596054
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.932658600
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2631876277
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2880316348
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.944340960
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.405032206
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771490959
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3191736496
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.68123866
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1986766098
/workspace/coverage/default/53.chip_sw_all_escalation_resets.946223820
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2274518655
/workspace/coverage/default/54.chip_sw_all_escalation_resets.607199307
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.805442236
/workspace/coverage/default/55.chip_sw_all_escalation_resets.542340149
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857542359
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2869513214
/workspace/coverage/default/58.chip_sw_all_escalation_resets.901132197
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3805914409
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3030893334
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2913394584
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.43552132
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4248870372
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.850101347
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3140618383
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741173882
/workspace/coverage/default/61.chip_sw_all_escalation_resets.113655822
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3474024484
/workspace/coverage/default/62.chip_sw_all_escalation_resets.4047989399
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351103047
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1595655301
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3660939409
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2497299932
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.32475632
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3703714975
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.234485993
/workspace/coverage/default/66.chip_sw_all_escalation_resets.944936587
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765060987
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1257286603
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3904451226
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333066108
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4097391248
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2389715085
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.375323914
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2008245424
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.260494888
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3745579969
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4269999095
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1031985144
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2145559639
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1942931911
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.260759300
/workspace/coverage/default/73.chip_sw_all_escalation_resets.829298584
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834845394
/workspace/coverage/default/74.chip_sw_all_escalation_resets.461396006
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2394454878
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3307318097
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336400342
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4104189406
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2876027872
/workspace/coverage/default/77.chip_sw_all_escalation_resets.18464240
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277455016
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2464124617
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627490307
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3422320903
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2247586334
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2576458413
/workspace/coverage/default/80.chip_sw_all_escalation_resets.990531253
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1351680654
/workspace/coverage/default/81.chip_sw_all_escalation_resets.592535427
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1462657345
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3377706625
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4236024168
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333505415
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1829534309
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.827446871
/workspace/coverage/default/85.chip_sw_all_escalation_resets.58082861
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.993782300
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3483551048
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151347687
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3035980630
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2486493713
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426912029
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1537809568
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2483195572
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1229499382
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2239623028
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2596386832
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3763033005
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3629585447
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2671209350
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1409232059
/workspace/coverage/default/96.chip_sw_all_escalation_resets.653590
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2897463729
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3127234460
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1188582899
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2397105215
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.381411368
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.639818567
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.991632768
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2457085967
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3702765200

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Total test records in report: 2870

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3891946960			Jun 26 08:03:08 PM PDT 24	Jun 26 08:09:16 PM PDT 24	2891333118 ps
T5	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2717304768			Jun 26 07:57:30 PM PDT 24	Jun 26 08:20:30 PM PDT 24	8209357642 ps
T6	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4269999095			Jun 26 08:27:49 PM PDT 24	Jun 26 08:33:03 PM PDT 24	3657508816 ps
T17	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3530306674			Jun 26 07:57:35 PM PDT 24	Jun 26 08:06:05 PM PDT 24	4774518720 ps
T43	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3451973197			Jun 26 08:13:17 PM PDT 24	Jun 26 08:23:43 PM PDT 24	5909104680 ps
T86	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1621246959			Jun 26 08:08:57 PM PDT 24	Jun 26 08:27:18 PM PDT 24	7241999248 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3395039328			Jun 26 08:08:22 PM PDT 24	Jun 26 08:16:18 PM PDT 24	8105365338 ps
T59	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1881444495			Jun 26 08:06:08 PM PDT 24	Jun 26 08:18:05 PM PDT 24	3707540360 ps
T87	/workspace/coverage/default/2.chip_sw_aes_entropy.2384110138			Jun 26 08:14:25 PM PDT 24	Jun 26 08:18:01 PM PDT 24	2425486688 ps
T88	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1761627477			Jun 26 08:07:05 PM PDT 24	Jun 26 08:12:16 PM PDT 24	2354778916 ps
T99	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151347687			Jun 26 08:29:14 PM PDT 24	Jun 26 08:36:50 PM PDT 24	3340350232 ps
T44	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3479115922			Jun 26 08:07:49 PM PDT 24	Jun 26 08:16:16 PM PDT 24	4825212766 ps
T100	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4204901962			Jun 26 08:29:04 PM PDT 24	Jun 26 08:34:33 PM PDT 24	4022951804 ps
T101	/workspace/coverage/default/0.chip_sw_kmac_smoketest.1533276963			Jun 26 08:04:56 PM PDT 24	Jun 26 08:09:28 PM PDT 24	2469775582 ps
T18	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1496608883			Jun 26 08:05:43 PM PDT 24	Jun 26 08:18:05 PM PDT 24	6795278112 ps
T102	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1378836551			Jun 26 08:03:40 PM PDT 24	Jun 26 08:09:28 PM PDT 24	4792298920 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3955397610			Jun 26 07:54:24 PM PDT 24	Jun 26 08:08:39 PM PDT 24	8980475000 ps
T63	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2590518764			Jun 26 08:21:43 PM PDT 24	Jun 26 08:34:15 PM PDT 24	4818202868 ps
T646	/workspace/coverage/default/1.chip_sw_csrng_smoketest.3200552827			Jun 26 08:10:57 PM PDT 24	Jun 26 08:15:19 PM PDT 24	2678156502 ps
T107	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3002512364			Jun 26 08:20:54 PM PDT 24	Jun 26 08:26:34 PM PDT 24	2874873780 ps
T135	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2315870683			Jun 26 08:24:12 PM PDT 24	Jun 26 08:46:27 PM PDT 24	8729479358 ps
T20	/workspace/coverage/default/1.chip_jtag_mem_access.1542267364			Jun 26 07:59:59 PM PDT 24	Jun 26 08:22:43 PM PDT 24	13844999595 ps
T54	/workspace/coverage/default/1.rom_e2e_asm_init_rma.4064174540			Jun 26 08:14:23 PM PDT 24	Jun 26 09:21:06 PM PDT 24	14502052273 ps
T387	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655179645			Jun 26 08:30:32 PM PDT 24	Jun 26 08:37:38 PM PDT 24	3523467260 ps
T64	/workspace/coverage/default/46.chip_sw_all_escalation_resets.20183654			Jun 26 08:26:41 PM PDT 24	Jun 26 08:38:42 PM PDT 24	4746545400 ps
T65	/workspace/coverage/default/88.chip_sw_all_escalation_resets.2486493713			Jun 26 08:29:06 PM PDT 24	Jun 26 08:38:30 PM PDT 24	5169720340 ps
T29	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2889140985			Jun 26 07:53:32 PM PDT 24	Jun 26 08:02:18 PM PDT 24	3839449750 ps
T116	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.639045358			Jun 26 08:12:47 PM PDT 24	Jun 26 08:19:23 PM PDT 24	6155650000 ps
T388	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2345460274			Jun 26 08:16:18 PM PDT 24	Jun 26 08:19:26 PM PDT 24	2461915256 ps
T171	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3191736496			Jun 26 08:26:38 PM PDT 24	Jun 26 08:34:45 PM PDT 24	4741299336 ps
T55	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1106172601			Jun 26 08:15:28 PM PDT 24	Jun 26 09:10:55 PM PDT 24	15129660368 ps
T30	/workspace/coverage/default/0.chip_sw_usbdev_stream.1015939781			Jun 26 07:57:16 PM PDT 24	Jun 26 09:11:17 PM PDT 24	19431967304 ps
T104	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3412253479			Jun 26 08:09:11 PM PDT 24	Jun 26 09:27:14 PM PDT 24	24787288821 ps
T155	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.4006584528			Jun 26 08:12:52 PM PDT 24	Jun 26 08:22:20 PM PDT 24	5669206501 ps
T296	/workspace/coverage/default/2.chip_plic_all_irqs_20.3852208299			Jun 26 08:24:00 PM PDT 24	Jun 26 08:37:57 PM PDT 24	4643855678 ps
T140	/workspace/coverage/default/1.chip_plic_all_irqs_10.510824806			Jun 26 08:05:27 PM PDT 24	Jun 26 08:14:20 PM PDT 24	3451855160 ps
T686	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3061047467			Jun 26 07:57:16 PM PDT 24	Jun 26 08:06:59 PM PDT 24	4949353272 ps
T212	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2702757536			Jun 26 08:26:45 PM PDT 24	Jun 26 08:32:21 PM PDT 24	3377819092 ps
T505	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2484194779			Jun 26 08:20:15 PM PDT 24	Jun 26 08:33:28 PM PDT 24	5782902264 ps
T57	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1233172506			Jun 26 08:22:22 PM PDT 24	Jun 26 08:37:21 PM PDT 24	13078466625 ps
T311	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1487344954			Jun 26 08:15:08 PM PDT 24	Jun 26 08:19:07 PM PDT 24	3209102384 ps
T331	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4169735487			Jun 26 07:58:30 PM PDT 24	Jun 26 08:04:26 PM PDT 24	2889387812 ps
T58	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.394551112			Jun 26 08:01:13 PM PDT 24	Jun 26 08:17:47 PM PDT 24	9318967969 ps
T167	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.673334795			Jun 26 07:57:41 PM PDT 24	Jun 26 08:01:23 PM PDT 24	2935976232 ps
T289	/workspace/coverage/default/0.chip_sw_aes_entropy.4236951624			Jun 26 07:57:46 PM PDT 24	Jun 26 08:02:39 PM PDT 24	3033793436 ps
T84	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1600662866			Jun 26 08:10:55 PM PDT 24	Jun 26 11:11:51 PM PDT 24	65849183356 ps
T2	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2349652734			Jun 26 07:58:15 PM PDT 24	Jun 26 08:03:56 PM PDT 24	3538283336 ps
T290	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1660419490			Jun 26 08:17:19 PM PDT 24	Jun 26 08:20:49 PM PDT 24	2653927982 ps
T113	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2509710563			Jun 26 08:06:18 PM PDT 24	Jun 26 08:15:30 PM PDT 24	6230644500 ps
T110	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1296517100			Jun 26 08:16:15 PM PDT 24	Jun 26 08:29:26 PM PDT 24	3996649418 ps
T250	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1632582381			Jun 26 08:04:46 PM PDT 24	Jun 26 09:00:39 PM PDT 24	26052133466 ps
T291	/workspace/coverage/default/50.chip_sw_all_escalation_resets.827330590			Jun 26 08:26:23 PM PDT 24	Jun 26 08:34:08 PM PDT 24	4767588500 ps
T70	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2030720522			Jun 26 08:00:37 PM PDT 24	Jun 26 08:53:37 PM PDT 24	26987432025 ps
T264	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.566972057			Jun 26 08:05:00 PM PDT 24	Jun 26 08:15:16 PM PDT 24	9302418388 ps
T234	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2191495998			Jun 26 08:20:40 PM PDT 24	Jun 26 08:34:26 PM PDT 24	6605583080 ps
T202	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3320143364			Jun 26 08:11:38 PM PDT 24	Jun 26 08:26:56 PM PDT 24	4860093948 ps
T69	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1938753667			Jun 26 07:56:02 PM PDT 24	Jun 26 08:03:40 PM PDT 24	4643624283 ps
T269	/workspace/coverage/default/1.chip_sw_otbn_randomness.4093873368			Jun 26 08:05:15 PM PDT 24	Jun 26 08:25:15 PM PDT 24	5862878064 ps
T27	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2576385327			Jun 26 08:12:34 PM PDT 24	Jun 26 08:23:15 PM PDT 24	3704745840 ps
T251	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4215916956			Jun 26 08:12:34 PM PDT 24	Jun 26 08:38:05 PM PDT 24	12586797802 ps
T151	/workspace/coverage/default/0.chip_sival_flash_info_access.2138825277			Jun 26 07:54:33 PM PDT 24	Jun 26 07:59:39 PM PDT 24	2740311926 ps
T144	/workspace/coverage/default/2.chip_sw_all_escalation_resets.678855910			Jun 26 08:11:31 PM PDT 24	Jun 26 08:21:23 PM PDT 24	4949926386 ps
T149	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.540428347			Jun 26 07:53:51 PM PDT 24	Jun 26 07:55:54 PM PDT 24	2086251555 ps
T270	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3805914409			Jun 26 08:27:00 PM PDT 24	Jun 26 08:37:22 PM PDT 24	4824756688 ps
T238	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.938056077			Jun 26 08:01:32 PM PDT 24	Jun 26 08:08:56 PM PDT 24	5440079206 ps
T85	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1492960342			Jun 26 08:11:41 PM PDT 24	Jun 27 12:19:58 AM PDT 24	78943441640 ps
T239	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4048619003			Jun 26 08:06:34 PM PDT 24	Jun 26 08:13:32 PM PDT 24	4957538872 ps
T420	/workspace/coverage/default/2.chip_sw_kmac_entropy.21297944			Jun 26 08:12:13 PM PDT 24	Jun 26 08:16:01 PM PDT 24	2360328848 ps
T367	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2937080589			Jun 26 08:28:12 PM PDT 24	Jun 26 08:37:04 PM PDT 24	4895915880 ps
T162	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.189680346			Jun 26 07:54:49 PM PDT 24	Jun 26 07:57:35 PM PDT 24	3305218330 ps
T111	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.554616849			Jun 26 08:20:34 PM PDT 24	Jun 26 08:37:37 PM PDT 24	8173472984 ps
T159	/workspace/coverage/default/0.chip_sw_flash_init.3624760993			Jun 26 07:53:34 PM PDT 24	Jun 26 08:32:24 PM PDT 24	21497308338 ps
T236	/workspace/coverage/default/26.chip_sw_all_escalation_resets.4157346738			Jun 26 08:25:28 PM PDT 24	Jun 26 08:33:51 PM PDT 24	5196285654 ps
T150	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2135785438			Jun 26 08:13:47 PM PDT 24	Jun 26 08:16:01 PM PDT 24	2432119529 ps
T56	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.533116418			Jun 26 08:02:55 PM PDT 24	Jun 26 09:12:55 PM PDT 24	15878881760 ps
T60	/workspace/coverage/default/0.chip_sw_alert_test.1069972250			Jun 26 07:54:40 PM PDT 24	Jun 26 08:01:29 PM PDT 24	3593009552 ps
T872	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1842216631			Jun 26 07:54:19 PM PDT 24	Jun 26 07:59:12 PM PDT 24	3253168090 ps
T385	/workspace/coverage/default/2.rom_e2e_asm_init_rma.1973453161			Jun 26 08:22:40 PM PDT 24	Jun 26 09:13:16 PM PDT 24	15092474500 ps
T677	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.414526560			Jun 26 08:04:46 PM PDT 24	Jun 26 08:10:44 PM PDT 24	3180267089 ps
T873	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.334915585			Jun 26 08:12:07 PM PDT 24	Jun 26 08:17:04 PM PDT 24	2516280680 ps
T48	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2799322645			Jun 26 08:14:30 PM PDT 24	Jun 26 08:21:56 PM PDT 24	5947412530 ps
T679	/workspace/coverage/default/1.chip_sw_hmac_oneshot.3069414080			Jun 26 08:06:11 PM PDT 24	Jun 26 08:13:24 PM PDT 24	4050691766 ps
T335	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.641826952			Jun 26 07:57:50 PM PDT 24	Jun 26 08:03:19 PM PDT 24	3231832545 ps
T221	/workspace/coverage/default/0.rom_keymgr_functest.4036312732			Jun 26 08:00:15 PM PDT 24	Jun 26 08:11:58 PM PDT 24	5711604208 ps
T390	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2720382613			Jun 26 08:31:55 PM PDT 24	Jun 26 08:39:14 PM PDT 24	5614146470 ps
T342	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1974584136			Jun 26 08:26:30 PM PDT 24	Jun 26 08:37:46 PM PDT 24	6274831524 ps
T874	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2259566876			Jun 26 08:24:14 PM PDT 24	Jun 26 08:33:19 PM PDT 24	4300421576 ps
T108	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1560708323			Jun 26 08:09:00 PM PDT 24	Jun 26 08:35:58 PM PDT 24	8604989615 ps
T875	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.836677679			Jun 26 07:59:21 PM PDT 24	Jun 26 08:07:30 PM PDT 24	3666615566 ps
T209	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2106459840			Jun 26 08:11:42 PM PDT 24	Jun 26 08:49:50 PM PDT 24	13264775220 ps
T876	/workspace/coverage/default/0.chip_sw_kmac_idle.889832854			Jun 26 07:56:21 PM PDT 24	Jun 26 08:00:40 PM PDT 24	2862503050 ps
T877	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1775454102			Jun 26 07:55:13 PM PDT 24	Jun 26 08:00:29 PM PDT 24	2666537869 ps
T184	/workspace/coverage/default/0.chip_tap_straps_dev.2387313937			Jun 26 07:56:29 PM PDT 24	Jun 26 08:03:00 PM PDT 24	4375653513 ps
T109	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1059094498			Jun 26 08:22:47 PM PDT 24	Jun 26 08:30:17 PM PDT 24	3692622017 ps
T105	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2536898046			Jun 26 08:20:30 PM PDT 24	Jun 26 09:12:33 PM PDT 24	24755677981 ps
T112	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3239757409			Jun 26 08:16:05 PM PDT 24	Jun 26 08:25:52 PM PDT 24	4403513928 ps
T24	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3186039306			Jun 26 08:01:06 PM PDT 24	Jun 26 08:09:49 PM PDT 24	4484612433 ps
T81	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.4242474517			Jun 26 07:57:26 PM PDT 24	Jun 26 08:04:07 PM PDT 24	3538710605 ps
T106	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3920976096			Jun 26 07:55:11 PM PDT 24	Jun 26 08:23:54 PM PDT 24	8453012752 ps
T252	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1451607974			Jun 26 07:57:10 PM PDT 24	Jun 26 08:46:21 PM PDT 24	21540588274 ps
T277	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3949756126			Jun 26 08:07:39 PM PDT 24	Jun 26 09:37:59 PM PDT 24	23228398180 ps
T136	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1909007457			Jun 26 08:19:56 PM PDT 24	Jun 26 08:31:17 PM PDT 24	4380538020 ps
T153	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2314063180			Jun 26 08:26:04 PM PDT 24	Jun 26 08:36:52 PM PDT 24	5794810696 ps
T31	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3651709181			Jun 26 08:10:36 PM PDT 24	Jun 26 08:20:08 PM PDT 24	5530042640 ps
T697	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2289142849			Jun 26 08:20:32 PM PDT 24	Jun 26 08:27:19 PM PDT 24	3390860136 ps
T878	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.125061273			Jun 26 08:08:46 PM PDT 24	Jun 26 08:13:46 PM PDT 24	2729104556 ps
T336	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2972665329			Jun 26 08:23:41 PM PDT 24	Jun 26 08:56:45 PM PDT 24	8502833544 ps
T213	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1684839286			Jun 26 08:00:55 PM PDT 24	Jun 26 08:21:32 PM PDT 24	8724572624 ps
T365	/workspace/coverage/default/0.rom_e2e_asm_init_prod.2904120186			Jun 26 08:05:20 PM PDT 24	Jun 26 09:12:59 PM PDT 24	16034705528 ps
T163	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1362406307			Jun 26 08:01:27 PM PDT 24	Jun 26 08:05:20 PM PDT 24	3377167555 ps
T373	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333066108			Jun 26 08:21:06 PM PDT 24	Jun 26 08:27:43 PM PDT 24	4012602808 ps
T337	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3307318097			Jun 26 08:28:05 PM PDT 24	Jun 26 08:37:22 PM PDT 24	5859159240 ps
T680	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1537809568			Jun 26 08:22:11 PM PDT 24	Jun 26 08:29:22 PM PDT 24	3663343284 ps
T114	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.397324799			Jun 26 07:56:36 PM PDT 24	Jun 26 08:22:11 PM PDT 24	7528557526 ps
T506	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3113500776			Jun 26 08:11:12 PM PDT 24	Jun 26 08:15:40 PM PDT 24	2419197240 ps
T307	/workspace/coverage/default/0.chip_plic_all_irqs_20.1143638164			Jun 26 08:02:48 PM PDT 24	Jun 26 08:18:18 PM PDT 24	4888416240 ps
T214	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4262757193			Jun 26 08:13:28 PM PDT 24	Jun 26 08:34:00 PM PDT 24	7192769380 ps
T145	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.850070499			Jun 26 08:15:30 PM PDT 24	Jun 26 11:54:07 PM PDT 24	254642774980 ps
T366	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2046648440			Jun 26 08:05:15 PM PDT 24	Jun 26 10:04:58 PM PDT 24	24129651094 ps
T759	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3035980630			Jun 26 08:29:06 PM PDT 24	Jun 26 08:35:55 PM PDT 24	3710047146 ps
T879	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2733428595			Jun 26 08:24:16 PM PDT 24	Jun 26 08:57:07 PM PDT 24	13377416364 ps
T341	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2167343736			Jun 26 08:25:14 PM PDT 24	Jun 26 08:35:35 PM PDT 24	5357801720 ps
T880	/workspace/coverage/default/1.chip_sw_example_concurrency.2204459061			Jun 26 08:00:10 PM PDT 24	Jun 26 08:03:57 PM PDT 24	2433740106 ps
T881	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3847081351			Jun 26 08:00:53 PM PDT 24	Jun 26 08:09:06 PM PDT 24	7428091100 ps
T241	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2876027872			Jun 26 08:28:51 PM PDT 24	Jun 26 08:33:31 PM PDT 24	3579610872 ps
T279	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2369968788			Jun 26 08:19:05 PM PDT 24	Jun 26 08:22:50 PM PDT 24	2863166286 ps
T280	/workspace/coverage/default/99.chip_sw_all_escalation_resets.2897463729			Jun 26 08:29:11 PM PDT 24	Jun 26 08:37:20 PM PDT 24	4968032694 ps
T281	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2189168168			Jun 26 07:58:50 PM PDT 24	Jun 26 08:17:48 PM PDT 24	7415094166 ps
T282	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.226741133			Jun 26 08:27:32 PM PDT 24	Jun 26 08:35:05 PM PDT 24	4162488702 ps
T28	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3390113490			Jun 26 08:20:48 PM PDT 24	Jun 26 08:26:07 PM PDT 24	2801634768 ps
T137	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2116129883			Jun 26 08:15:26 PM PDT 24	Jun 26 09:06:49 PM PDT 24	18902634125 ps
T283	/workspace/coverage/default/1.chip_tap_straps_prod.3929513234			Jun 26 08:07:57 PM PDT 24	Jun 26 08:10:26 PM PDT 24	2868485166 ps
T284	/workspace/coverage/default/98.chip_sw_all_escalation_resets.1726722457			Jun 26 08:29:26 PM PDT 24	Jun 26 08:39:45 PM PDT 24	5630766954 ps
T285	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3576623663			Jun 26 08:13:33 PM PDT 24	Jun 26 08:16:50 PM PDT 24	2738162032 ps
T71	/workspace/coverage/default/1.chip_jtag_csr_rw.1814235860			Jun 26 07:59:59 PM PDT 24	Jun 26 08:22:52 PM PDT 24	10883306715 ps
T176	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.779755993			Jun 26 08:21:44 PM PDT 24	Jun 26 08:28:48 PM PDT 24	5307207959 ps
T347	/workspace/coverage/default/1.chip_sival_flash_info_access.3143593541			Jun 26 07:58:45 PM PDT 24	Jun 26 08:04:57 PM PDT 24	3087274464 ps
T882	/workspace/coverage/default/1.chip_sw_kmac_idle.828641271			Jun 26 08:04:37 PM PDT 24	Jun 26 08:09:17 PM PDT 24	3423118750 ps
T49	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3559212570			Jun 26 07:55:13 PM PDT 24	Jun 26 08:03:51 PM PDT 24	5778321680 ps
T883	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3185422776			Jun 26 08:01:10 PM PDT 24	Jun 26 08:18:34 PM PDT 24	5282432840 ps
T215	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2193070257			Jun 26 08:16:58 PM PDT 24	Jun 26 08:33:41 PM PDT 24	6733617640 ps
T884	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.711020015			Jun 26 07:55:39 PM PDT 24	Jun 26 09:00:25 PM PDT 24	19799854386 ps
T704	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.516476330			Jun 26 08:18:53 PM PDT 24	Jun 26 08:27:38 PM PDT 24	3819426968 ps
T323	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1936426953			Jun 26 08:11:48 PM PDT 24	Jun 26 08:24:23 PM PDT 24	4479518040 ps
T885	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3117198087			Jun 26 08:14:48 PM PDT 24	Jun 26 08:37:52 PM PDT 24	6049915349 ps
T143	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3374683600			Jun 26 07:56:53 PM PDT 24	Jun 26 08:08:36 PM PDT 24	5524023232 ps
T690	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2588497088			Jun 26 08:26:00 PM PDT 24	Jun 26 08:35:16 PM PDT 24	4507182360 ps
T681	/workspace/coverage/default/53.chip_sw_all_escalation_resets.946223820			Jun 26 08:28:05 PM PDT 24	Jun 26 08:36:45 PM PDT 24	5134688300 ps
T193	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3385725245			Jun 26 08:14:08 PM PDT 24	Jun 26 08:26:06 PM PDT 24	5127880545 ps
T160	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3531741908			Jun 26 08:01:06 PM PDT 24	Jun 26 08:09:37 PM PDT 24	5748507170 ps
T886	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1892638935			Jun 26 08:13:24 PM PDT 24	Jun 26 08:20:36 PM PDT 24	4161197458 ps
T117	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4105933408			Jun 26 08:06:36 PM PDT 24	Jun 26 08:14:20 PM PDT 24	5630679014 ps
T678	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.805442236			Jun 26 08:29:44 PM PDT 24	Jun 26 08:36:40 PM PDT 24	3811511760 ps
T887	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1446976175			Jun 26 08:01:38 PM PDT 24	Jun 26 08:18:05 PM PDT 24	5838228755 ps
T194	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1613201096			Jun 26 07:56:13 PM PDT 24	Jun 26 08:00:20 PM PDT 24	3218896555 ps
T888	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2576767802			Jun 26 08:12:59 PM PDT 24	Jun 26 08:22:38 PM PDT 24	7130252436 ps
T889	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.879815873			Jun 26 08:04:45 PM PDT 24	Jun 26 08:08:06 PM PDT 24	2652478302 ps
T392	/workspace/coverage/default/60.chip_sw_all_escalation_resets.258158969			Jun 26 08:26:34 PM PDT 24	Jun 26 08:36:20 PM PDT 24	4931230408 ps
T371	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.966864009			Jun 26 08:00:13 PM PDT 24	Jun 26 08:03:57 PM PDT 24	3167244222 ps
T152	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3980809873			Jun 26 07:56:07 PM PDT 24	Jun 26 09:42:15 PM PDT 24	50438204030 ps
T890	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4037181965			Jun 26 08:13:14 PM PDT 24	Jun 26 09:00:29 PM PDT 24	45067446998 ps
T747	/workspace/coverage/default/11.chip_sw_all_escalation_resets.371017493			Jun 26 08:23:45 PM PDT 24	Jun 26 08:36:32 PM PDT 24	4904485428 ps
T225	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2271393147			Jun 26 08:08:12 PM PDT 24	Jun 26 08:45:14 PM PDT 24	20651692399 ps
T891	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.609552421			Jun 26 08:02:51 PM PDT 24	Jun 26 08:10:31 PM PDT 24	4047942800 ps
T892	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3647634767			Jun 26 08:20:50 PM PDT 24	Jun 26 08:29:37 PM PDT 24	6719349900 ps
T235	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.557672135			Jun 26 08:12:58 PM PDT 24	Jun 26 08:22:06 PM PDT 24	4280258012 ps
T386	/workspace/coverage/default/1.rom_e2e_static_critical.2374908829			Jun 26 08:14:31 PM PDT 24	Jun 26 09:19:21 PM PDT 24	16693755816 ps
T297	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4240649449			Jun 26 08:25:09 PM PDT 24	Jun 26 08:31:50 PM PDT 24	4454302876 ps
T173	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3481052657			Jun 26 08:12:40 PM PDT 24	Jun 26 09:35:11 PM PDT 24	43309191138 ps
T303	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1422759742			Jun 26 07:58:07 PM PDT 24	Jun 26 08:04:52 PM PDT 24	5106737700 ps
T72	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1121196570			Jun 26 07:57:57 PM PDT 24	Jun 26 10:56:39 PM PDT 24	58141185494 ps
T248	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.532621733			Jun 26 08:11:58 PM PDT 24	Jun 26 08:16:23 PM PDT 24	3410211520 ps
T304	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3030893334			Jun 26 08:20:56 PM PDT 24	Jun 26 08:27:46 PM PDT 24	2971446860 ps
T3	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4276358786			Jun 26 08:10:29 PM PDT 24	Jun 26 08:17:05 PM PDT 24	2999977772 ps
T305	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2598917116			Jun 26 07:55:11 PM PDT 24	Jun 26 08:17:07 PM PDT 24	6071474723 ps
T306	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1839096134			Jun 26 08:04:59 PM PDT 24	Jun 26 08:10:35 PM PDT 24	3034189498 ps
T66	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2264646432			Jun 26 08:19:50 PM PDT 24	Jun 26 08:22:49 PM PDT 24	2773865273 ps
T203	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4153104872			Jun 26 08:19:38 PM PDT 24	Jun 26 09:07:07 PM PDT 24	13217125608 ps
T205	/workspace/coverage/default/2.chip_sw_pattgen_ios.2463779892			Jun 26 08:10:20 PM PDT 24	Jun 26 08:15:10 PM PDT 24	2870964554 ps
T257	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.722674957			Jun 26 08:15:16 PM PDT 24	Jun 26 08:34:30 PM PDT 24	6973975738 ps
T406	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.970743047			Jun 26 08:24:25 PM PDT 24	Jun 26 08:30:24 PM PDT 24	4234133024 ps
T407	/workspace/coverage/default/1.chip_sw_hmac_smoketest.4021121048			Jun 26 08:10:27 PM PDT 24	Jun 26 08:15:57 PM PDT 24	2729972800 ps
T408	/workspace/coverage/default/5.chip_sw_all_escalation_resets.340274551			Jun 26 08:20:53 PM PDT 24	Jun 26 08:32:42 PM PDT 24	5138970832 ps
T309	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2319887353			Jun 26 08:24:48 PM PDT 24	Jun 26 08:59:00 PM PDT 24	13442523282 ps
T421	/workspace/coverage/default/0.chip_sw_kmac_entropy.3993035163			Jun 26 07:54:06 PM PDT 24	Jun 26 07:58:58 PM PDT 24	2788055734 ps
T237	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1157428733			Jun 26 07:54:41 PM PDT 24	Jun 26 08:06:38 PM PDT 24	6528653732 ps
T175	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.18698782			Jun 26 08:05:37 PM PDT 24	Jun 26 08:12:39 PM PDT 24	3560052372 ps
T7	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1379994189			Jun 26 08:07:25 PM PDT 24	Jun 26 08:36:00 PM PDT 24	22247736008 ps
T893	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3880012086			Jun 26 08:18:11 PM PDT 24	Jun 26 08:21:12 PM PDT 24	2115378088 ps
T748	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3080942015			Jun 26 08:25:49 PM PDT 24	Jun 26 08:31:32 PM PDT 24	3830967448 ps
T380	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2732933633			Jun 26 08:16:43 PM PDT 24	Jun 26 08:46:12 PM PDT 24	10765070728 ps
T894	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.761557680			Jun 26 08:24:42 PM PDT 24	Jun 26 08:34:07 PM PDT 24	6284018407 ps
T701	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2417451374			Jun 26 07:59:21 PM PDT 24	Jun 26 08:11:28 PM PDT 24	4769602200 ps
T895	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.466959084			Jun 26 07:57:04 PM PDT 24	Jun 26 08:06:59 PM PDT 24	4808204020 ps
T249	/workspace/coverage/default/2.chip_sw_rv_timer_irq.532349004			Jun 26 08:13:02 PM PDT 24	Jun 26 08:17:24 PM PDT 24	3182597640 ps
T368	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301274644			Jun 26 08:25:54 PM PDT 24	Jun 26 08:33:06 PM PDT 24	3678016882 ps
T168	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1152155311			Jun 26 08:07:20 PM PDT 24	Jun 26 08:13:45 PM PDT 24	2890296744 ps
T15	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2340328905			Jun 26 07:57:29 PM PDT 24	Jun 26 08:03:17 PM PDT 24	7506834190 ps
T204	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3416188375			Jun 26 08:10:55 PM PDT 24	Jun 26 08:22:07 PM PDT 24	4231109480 ps
T376	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1102402728			Jun 26 08:24:51 PM PDT 24	Jun 26 08:30:43 PM PDT 24	3403586066 ps
T377	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3703714975			Jun 26 08:27:29 PM PDT 24	Jun 26 08:38:55 PM PDT 24	4585934156 ps
T211	/workspace/coverage/default/3.chip_tap_straps_dev.228681135			Jun 26 08:20:22 PM PDT 24	Jun 26 08:26:49 PM PDT 24	4102463239 ps
T332	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3426405457			Jun 26 08:00:55 PM PDT 24	Jun 26 08:10:40 PM PDT 24	3957173300 ps
T378	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1412098891			Jun 26 08:15:27 PM PDT 24	Jun 26 08:20:39 PM PDT 24	2976959504 ps
T217	/workspace/coverage/default/83.chip_sw_all_escalation_resets.4236024168			Jun 26 08:29:22 PM PDT 24	Jun 26 08:39:29 PM PDT 24	5651071420 ps
T379	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771490959			Jun 26 08:26:32 PM PDT 24	Jun 26 08:34:37 PM PDT 24	3724700760 ps
T82	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.855697949			Jun 26 08:14:11 PM PDT 24	Jun 26 08:37:34 PM PDT 24	12288524440 ps
T165	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3877645986			Jun 26 08:09:34 PM PDT 24	Jun 26 08:18:51 PM PDT 24	4863513902 ps
T896	/workspace/coverage/default/2.chip_sival_flash_info_access.418343754			Jun 26 08:11:23 PM PDT 24	Jun 26 08:15:40 PM PDT 24	3102421860 ps
T897	/workspace/coverage/default/0.chip_sw_hmac_smoketest.248813428			Jun 26 08:00:20 PM PDT 24	Jun 26 08:05:31 PM PDT 24	3416462344 ps
T898	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1176816301			Jun 26 08:06:22 PM PDT 24	Jun 26 08:36:23 PM PDT 24	9083156152 ps
T706	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1257286603			Jun 26 08:26:54 PM PDT 24	Jun 26 08:38:02 PM PDT 24	5542975128 ps
T254	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2813016145			Jun 26 08:20:32 PM PDT 24	Jun 26 09:03:11 PM PDT 24	10942429900 ps
T712	/workspace/coverage/default/66.chip_sw_all_escalation_resets.944936587			Jun 26 08:27:04 PM PDT 24	Jun 26 08:35:46 PM PDT 24	5863716688 ps
T265	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2769762262			Jun 26 08:16:00 PM PDT 24	Jun 26 08:23:44 PM PDT 24	8503606283 ps
T231	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2788930448			Jun 26 07:54:34 PM PDT 24	Jun 26 08:03:23 PM PDT 24	5735104768 ps
T35	/workspace/coverage/default/0.chip_sw_usbdev_dpi.82208729			Jun 26 07:57:43 PM PDT 24	Jun 26 08:49:34 PM PDT 24	12545386820 ps
T899	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2482828406			Jun 26 08:04:39 PM PDT 24	Jun 26 08:11:48 PM PDT 24	6315423930 ps
T702	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1718365384			Jun 26 08:11:09 PM PDT 24	Jun 26 08:20:23 PM PDT 24	5695793456 ps
T900	/workspace/coverage/default/0.chip_sw_flash_crash_alert.610556272			Jun 26 07:57:42 PM PDT 24	Jun 26 08:07:47 PM PDT 24	5453454224 ps
T901	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1458753031			Jun 26 08:04:48 PM PDT 24	Jun 26 09:06:26 PM PDT 24	15744134944 ps
T50	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3928065920			Jun 26 08:03:46 PM PDT 24	Jun 26 08:11:03 PM PDT 24	5411687516 ps
T902	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3658874104			Jun 26 08:23:44 PM PDT 24	Jun 26 09:03:35 PM PDT 24	12546944952 ps
T324	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.314922226			Jun 26 08:18:48 PM PDT 24	Jun 26 08:30:30 PM PDT 24	4474713152 ps
T689	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1290160925			Jun 26 08:15:35 PM PDT 24	Jun 26 08:35:41 PM PDT 24	8377969090 ps
T903	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1295742437			Jun 26 08:11:07 PM PDT 24	Jun 26 08:15:57 PM PDT 24	3454309096 ps
T792	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1781751858			Jun 26 08:21:29 PM PDT 24	Jun 26 08:31:06 PM PDT 24	5637738050 ps
T904	/workspace/coverage/default/2.chip_sw_otbn_randomness.3691033806			Jun 26 08:13:14 PM PDT 24	Jun 26 08:30:04 PM PDT 24	5427595272 ps
T161	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2933574389			Jun 26 08:01:02 PM PDT 24	Jun 26 09:34:13 PM PDT 24	50698174390 ps
T905	/workspace/coverage/default/2.chip_sw_example_rom.399233880			Jun 26 08:12:47 PM PDT 24	Jun 26 08:14:59 PM PDT 24	2669340338 ps
T906	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.850101347			Jun 26 08:23:38 PM PDT 24	Jun 26 08:32:53 PM PDT 24	3468162260 ps
T216	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.772554974			Jun 26 08:01:53 PM PDT 24	Jun 26 08:21:44 PM PDT 24	7352342844 ps
T353	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2312746452			Jun 26 08:25:30 PM PDT 24	Jun 26 08:32:18 PM PDT 24	4003880072 ps
T355	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1748957172			Jun 26 08:24:44 PM PDT 24	Jun 26 08:33:01 PM PDT 24	3512716972 ps
T166	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1979469076			Jun 26 08:18:11 PM PDT 24	Jun 26 08:27:16 PM PDT 24	5386003742 ps
T356	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3511121003			Jun 26 08:17:58 PM PDT 24	Jun 26 08:21:39 PM PDT 24	3229406652 ps
T357	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.32475632			Jun 26 08:27:03 PM PDT 24	Jun 26 08:34:00 PM PDT 24	3310281490 ps
T195	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1966523907			Jun 26 08:03:41 PM PDT 24	Jun 26 08:14:42 PM PDT 24	4494708694 ps
T358	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2182538974			Jun 26 08:20:01 PM PDT 24	Jun 26 08:30:01 PM PDT 24	4117750272 ps
T255	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1591906633			Jun 26 08:20:28 PM PDT 24	Jun 26 09:36:55 PM PDT 24	16416698328 ps
T359	/workspace/coverage/default/0.chip_sw_uart_smoketest.458575644			Jun 26 07:58:11 PM PDT 24	Jun 26 08:02:16 PM PDT 24	2520171816 ps
T227	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3435986611			Jun 26 07:56:29 PM PDT 24	Jun 26 08:30:54 PM PDT 24	22869299499 ps
T907	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1208592383			Jun 26 08:18:21 PM PDT 24	Jun 26 08:31:19 PM PDT 24	4134635000 ps
T908	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2239623028			Jun 26 08:21:44 PM PDT 24	Jun 26 08:32:10 PM PDT 24	4475906702 ps
T206	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.209815019			Jun 26 07:55:47 PM PDT 24	Jun 26 08:12:48 PM PDT 24	4662486442 ps
T764	/workspace/coverage/default/23.chip_sw_all_escalation_resets.660768376			Jun 26 08:23:55 PM PDT 24	Jun 26 08:32:55 PM PDT 24	4571133396 ps
T703	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3679555103			Jun 26 08:26:39 PM PDT 24	Jun 26 08:37:10 PM PDT 24	5557654880 ps
T705	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2758838226			Jun 26 08:00:57 PM PDT 24	Jun 26 08:10:07 PM PDT 24	3657396368 ps
T909	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3935329681			Jun 26 08:02:30 PM PDT 24	Jun 26 09:06:47 PM PDT 24	16075630440 ps
T83	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3723409098			Jun 26 08:04:45 PM PDT 24	Jun 26 08:25:58 PM PDT 24	11254140192 ps