Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133290	1			T74	89		T76	10		T78	3
values[2]	8927	1			T74	1		T80	146		T514	2
values[3]	3814	1			T80	29		T405	20		T396	3
values[4]	2392	1			T80	8		T405	21		T396	3
values[5]	1540	1			T80	14		T405	13		T396	3
values[6]	1179	1			T80	12		T405	12		T396	3
values[7]	805	1			T80	5		T405	10		T396	3
values[8]	554	1			T80	17		T405	8		T396	3
values[9]	434	1			T80	4		T405	3		T396	3
values[10]	323	1			T80	5		T405	1		T396	3
values[11]	306	1			T80	5		T405	4		T396	3
values[12]	330	1			T80	23		T405	2		T396	3
values[13]	253	1			T80	5		T405	2		T396	3
values[14]	243	1			T80	19		T405	1		T396	3
values[15]	275	1			T80	6		T405	3		T396	3
values[16]	300	1			T80	3		T405	5		T396	3
values[17]	271	1			T80	4		T405	1		T396	3
values[18]	269	1			T80	5		T405	2		T396	3
values[19]	275	1			T80	3		T405	1		T396	3
values[20]	266	1			T80	6		T405	1		T396	3
values[21]	226	1			T80	9		T405	8		T396	3
values[22]	254	1			T80	8		T405	2		T396	3
values[23]	255	1			T80	3		T405	3		T396	3
values[24]	327	1			T80	8		T405	1		T396	3
values[25]	313	1			T80	22		T396	3		T459	11
values[26]	287	1			T80	7		T396	3		T459	2
values[27]	291	1			T80	5		T396	3		T459	3
values[28]	219	1			T80	3		T396	3		T459	1
values[29]	268	1			T80	4		T396	4		T459	2
values[30]	264	1			T80	5		T396	3		T459	1
values[31]	234	1			T80	10		T396	3		T459	1
values[32]	234	1			T80	9		T396	3		T459	2
values[33]	270	1			T80	12		T396	3		T459	2
values[34]	225	1			T80	5		T396	3		T459	1
values[35]	208	1			T80	6		T396	3		T459	2
values[36]	239	1			T80	7		T396	3		T459	2
values[37]	248	1			T80	10		T396	3		T459	6
values[38]	224	1			T80	5		T396	3		T459	7
values[39]	296	1			T80	13		T396	3		T459	3
values[40]	232	1			T80	10		T396	3		T819	4
values[41]	213	1			T80	6		T396	3		T819	11
values[42]	239	1			T80	7		T396	3		T819	4
values[43]	195	1			T80	3		T396	3		T819	3
values[44]	239	1			T80	10		T396	3		T819	6
values[45]	246	1			T80	8		T396	3		T819	3
values[46]	221	1			T80	8		T396	3		T820	7
values[47]	206	1			T80	5		T396	4		T820	3
values[48]	224	1			T80	9		T396	3		T820	5
values[49]	224	1			T80	11		T396	3		T820	7
values[50]	239	1			T80	22		T396	3		T820	7
values[51]	229	1			T80	8		T396	3		T820	7
values[52]	184	1			T80	6		T396	3		T820	6
values[53]	226	1			T80	5		T396	3		T820	3
values[54]	203	1			T80	7		T396	3		T820	6
values[55]	201	1			T80	5		T396	3		T820	5
values[56]	213	1			T80	6		T396	3		T820	4
values[57]	206	1			T80	9		T396	3		T820	6
values[58]	182	1			T80	6		T396	3		T820	8
values[59]	173	1			T80	5		T396	3		T820	8
values[60]	191	1			T80	20		T396	3		T820	6
values[61]	151	1			T80	3		T396	3		T820	4
values[62]	147	1			T80	6		T396	3		T820	3
values[63]	138	1			T80	14		T396	3		T820	5
values[64]	126	1			T80	5		T396	3		T820	4
values[65]	149	1			T80	2		T396	3		T820	8
values[66]	149	1			T396	3		T820	7		T821	3
values[67]	165	1			T396	3		T820	26		T821	4
values[68]	129	1			T396	3		T820	13		T821	3
values[69]	155	1			T396	3		T820	16		T821	6
values[70]	121	1			T396	3		T820	9		T466	1
values[71]	129	1			T396	3		T820	11		T466	1
values[72]	104	1			T396	4		T820	2		T466	1
values[73]	90	1			T396	3		T466	1		T822	1
values[74]	65	1			T396	3		T466	1		T822	1
values[75]	70	1			T396	3		T466	1		T822	1
values[76]	65	1			T396	3		T466	1		T822	1
values[77]	75	1			T396	3		T466	1		T822	6
values[78]	100	1			T396	3		T466	1		T822	19
values[79]	80	1			T396	3		T466	1		T822	5
values[80]	74	1			T396	3		T466	1		T822	10
values[81]	77	1			T396	3		T466	1		T822	2
values[82]	92	1			T396	3		T466	5		T822	7
values[83]	70	1			T396	3		T466	2		T822	5
values[84]	91	1			T396	3		T466	4		T822	9
values[85]	76	1			T396	3		T466	3		T822	6
values[86]	72	1			T396	3		T466	1		T822	2
values[87]	70	1			T396	3		T466	3		T822	1
values[88]	77	1			T396	3		T466	1		T822	1
values[89]	60	1			T396	3		T466	2		T822	3
values[90]	83	1			T396	3		T466	9		T822	2
values[91]	84	1			T396	3		T466	1		T822	1
values[92]	96	1			T396	3		T466	3		T822	1
values[93]	88	1			T396	4		T466	6		T822	1
values[94]	67	1			T396	4		T466	3		T822	1
values[95]	84	1			T396	5		T466	2		T822	3
values[96]	79	1			T396	8		T466	1		T822	3
values[97]	93	1			T396	7		T466	2		T822	1
values[98]	78	1			T396	9		T466	3		T822	1
values[99]	102	1			T396	10		T466	3		T822	2
values[100]	79	1			T396	9		T466	3		T822	1
values[101]	79	1			T396	7		T466	4		T822	2
values[102]	92	1			T396	6		T466	3		T822	1
values[103]	77	1			T396	4		T466	4		T822	2
values[104]	70	1			T396	7		T466	2		T822	1
values[105]	62	1			T396	10		T466	2		T822	3
values[106]	72	1			T396	6		T466	4		T822	1
values[107]	65	1			T396	6		T466	2		T822	4
values[108]	77	1			T396	9		T466	1		T822	1
values[109]	79	1			T396	4		T466	1		T822	1
values[110]	69	1			T396	7		T466	2		T822	2
values[111]	75	1			T396	7		T466	1		T822	1
values[112]	74	1			T396	6		T466	1		T822	3
values[113]	66	1			T396	4		T466	2		T822	1
values[114]	78	1			T396	10		T466	1		T822	4
values[115]	67	1			T396	8		T466	1		T822	1
values[116]	59	1			T396	5		T466	1		T822	4
values[117]	79	1			T396	4		T466	2		T822	2
values[118]	82	1			T396	8		T466	1		T822	1
values[119]	80	1			T396	9		T466	1		T822	1
values[120]	88	1			T396	5		T466	1		T822	2
values[121]	76	1			T396	6		T466	1		T822	1
values[122]	84	1			T396	9		T466	4		T822	1
values[123]	68	1			T396	3		T466	1		T822	1
values[124]	81	1			T396	7		T466	2		T822	3
values[125]	71	1			T396	3		T466	2		T822	1
values[126]	82	1			T396	7		T466	3		T822	3
values[127]	926	1			T396	77		T466	35		T822	23
values[128]	9260	1			T396	914		T466	307		T822	254