Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	158127	1			T74	90		T76	13		T78	5
values[2]	3993	1			T74	2		T502	1		T508	2
values[3]	1835	1			T502	1		T714	1		T525	31
values[4]	1445	1			T502	1		T525	30		T396	1
values[5]	1114	1			T502	1		T525	19		T396	1
values[6]	1093	1			T502	1		T525	25		T396	1
values[7]	893	1			T502	1		T525	19		T396	1
values[8]	845	1			T502	1		T525	15		T396	1
values[9]	722	1			T502	1		T525	10		T396	1
values[10]	538	1			T502	1		T525	16		T396	1
values[11]	480	1			T502	1		T525	19		T396	1
values[12]	440	1			T502	1		T525	17		T396	1
values[13]	425	1			T502	1		T525	25		T396	1
values[14]	346	1			T502	1		T525	36		T396	1
values[15]	312	1			T502	1		T525	23		T396	1
values[16]	290	1			T502	1		T525	17		T396	1
values[17]	343	1			T502	1		T525	6		T396	1
values[18]	354	1			T502	1		T525	7		T396	1
values[19]	344	1			T502	1		T525	16		T396	1
values[20]	269	1			T502	1		T525	14		T396	1
values[21]	251	1			T502	1		T525	12		T396	2
values[22]	240	1			T502	1		T525	3		T396	1
values[23]	178	1			T502	1		T525	2		T396	1
values[24]	233	1			T502	1		T525	4		T396	1
values[25]	194	1			T502	1		T525	1		T396	1
values[26]	170	1			T502	1		T525	14		T396	1
values[27]	141	1			T502	1		T525	15		T396	1
values[28]	121	1			T502	1		T525	11		T396	1
values[29]	121	1			T502	1		T525	3		T396	1
values[30]	113	1			T502	1		T525	4		T396	1
values[31]	148	1			T502	1		T525	12		T396	1
values[32]	116	1			T502	1		T525	5		T396	1
values[33]	148	1			T502	1		T525	5		T396	1
values[34]	153	1			T502	1		T525	5		T396	1
values[35]	117	1			T502	1		T525	7		T396	1
values[36]	85	1			T502	1		T525	6		T396	1
values[37]	87	1			T502	1		T396	1		T664	2
values[38]	75	1			T502	1		T396	1		T664	2
values[39]	88	1			T502	1		T396	1		T664	3
values[40]	55	1			T502	1		T396	1		T664	1
values[41]	46	1			T502	1		T396	1		T664	3
values[42]	35	1			T502	1		T396	1		T664	3
values[43]	28	1			T502	1		T396	1		T664	1
values[44]	29	1			T502	1		T396	1		T664	3
values[45]	35	1			T502	1		T396	1		T664	2
values[46]	30	1			T502	1		T396	1		T664	1
values[47]	30	1			T502	1		T396	1		T664	5
values[48]	35	1			T502	1		T396	1		T664	4
values[49]	36	1			T502	1		T396	1		T664	5
values[50]	29	1			T502	1		T396	1		T664	2
values[51]	27	1			T502	1		T396	1		T664	1
values[52]	38	1			T502	1		T396	1		T664	1
values[53]	33	1			T502	1		T396	1		T664	6
values[54]	35	1			T502	1		T396	1		T664	4
values[55]	29	1			T502	1		T396	1		T664	2
values[56]	28	1			T502	1		T396	1		T664	3
values[57]	33	1			T502	1		T396	1		T664	2
values[58]	31	1			T502	1		T396	1		T664	2
values[59]	34	1			T502	1		T396	1		T664	4
values[60]	29	1			T502	1		T396	1		T664	3
values[61]	27	1			T502	1		T396	1		T664	1
values[62]	35	1			T502	1		T396	1		T664	2
values[63]	37	1			T502	1		T396	1		T664	8
values[64]	34	1			T502	1		T396	1		T664	4
values[65]	29	1			T502	1		T396	1		T664	3
values[66]	26	1			T502	1		T396	1		T664	1
values[67]	31	1			T502	1		T396	1		T664	2
values[68]	39	1			T502	1		T396	1		T664	8
values[69]	35	1			T502	1		T396	1		T664	2
values[70]	35	1			T502	1		T396	1		T664	1
values[71]	27	1			T502	1		T396	1		T664	1
values[72]	31	1			T502	1		T396	1		T664	2
values[73]	37	1			T502	1		T396	1		T664	2
values[74]	33	1			T502	1		T396	1		T664	1
values[75]	34	1			T502	1		T396	1		T664	5
values[76]	31	1			T502	1		T396	1		T664	2
values[77]	37	1			T502	1		T396	1		T664	6
values[78]	40	1			T502	1		T396	1		T664	5
values[79]	65	1			T502	1		T396	1		T664	9
values[80]	47	1			T502	1		T396	1		T664	3
values[81]	39	1			T502	1		T396	2		T664	1
values[82]	44	1			T502	1		T396	1		T664	2
values[83]	50	1			T502	1		T396	1		T664	1
values[84]	46	1			T502	1		T396	1		T664	5
values[85]	39	1			T502	1		T396	1		T664	1
values[86]	32	1			T502	1		T396	1		T664	2
values[87]	37	1			T502	1		T396	1		T664	3
values[88]	42	1			T502	1		T396	4		T664	4
values[89]	47	1			T502	1		T396	1		T664	6
values[90]	44	1			T502	1		T396	3		T664	5
values[91]	48	1			T502	1		T396	3		T664	6
values[92]	54	1			T502	1		T396	2		T664	6
values[93]	66	1			T502	1		T396	1		T664	4
values[94]	39	1			T502	1		T396	1		T664	1
values[95]	58	1			T502	1		T396	4		T664	5
values[96]	52	1			T502	1		T396	2		T664	4
values[97]	56	1			T502	1		T396	3		T664	5
values[98]	65	1			T502	1		T396	3		T664	5
values[99]	64	1			T502	1		T396	4		T664	5
values[100]	48	1			T502	1		T396	2		T664	4
values[101]	49	1			T502	1		T396	1		T664	4
values[102]	52	1			T502	1		T396	3		T664	4
values[103]	50	1			T502	1		T396	2		T664	1
values[104]	55	1			T502	1		T396	1		T664	8
values[105]	57	1			T502	1		T396	4		T664	7
values[106]	68	1			T502	1		T396	14		T664	14
values[107]	48	1			T502	1		T396	3		T664	5
values[108]	52	1			T502	1		T396	1		T664	5
values[109]	52	1			T502	1		T396	2		T664	3
values[110]	60	1			T502	1		T396	3		T664	2
values[111]	52	1			T502	1		T396	2		T664	4
values[112]	46	1			T502	1		T396	2		T664	9
values[113]	42	1			T502	1		T396	1		T664	6
values[114]	57	1			T502	1		T396	2		T664	6
values[115]	61	1			T502	1		T396	1		T664	10
values[116]	76	1			T502	4		T396	2		T664	5
values[117]	65	1			T502	2		T396	2		T664	6
values[118]	70	1			T502	1		T396	1		T664	8
values[119]	73	1			T502	2		T396	4		T664	8
values[120]	53	1			T502	1		T396	1		T664	5
values[121]	51	1			T502	1		T396	1		T664	6
values[122]	64	1			T502	2		T396	2		T664	8
values[123]	73	1			T502	4		T396	2		T664	6
values[124]	79	1			T502	4		T396	3		T664	4
values[125]	152	1			T502	5		T396	3		T664	14
values[126]	414	1			T502	14		T396	13		T664	9
values[127]	2354	1			T502	103		T396	106		T664	3
values[128]	4393	1			T502	167		T396	233		T447	9