Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135431	1			T74	80		T76	10		T78	7
values[2]	9054	1			T74	5		T502	1		T508	3
values[3]	3482	1			T502	1		T405	53		T525	64
values[4]	2006	1			T502	1		T405	29		T525	35
values[5]	1227	1			T502	1		T405	17		T525	15
values[6]	925	1			T502	1		T405	14		T525	5
values[7]	677	1			T502	1		T405	9		T396	2
values[8]	487	1			T502	1		T405	6		T396	2
values[9]	352	1			T502	1		T405	4		T396	2
values[10]	386	1			T502	1		T405	6		T396	3
values[11]	362	1			T502	1		T405	6		T396	2
values[12]	330	1			T502	1		T405	7		T396	2
values[13]	296	1			T502	1		T405	8		T396	2
values[14]	348	1			T502	1		T405	11		T396	2
values[15]	312	1			T502	1		T405	3		T396	2
values[16]	243	1			T502	1		T405	3		T396	2
values[17]	297	1			T502	1		T405	5		T396	2
values[18]	286	1			T502	1		T405	3		T396	2
values[19]	312	1			T502	1		T405	1		T396	2
values[20]	288	1			T502	1		T405	1		T396	2
values[21]	293	1			T502	1		T405	4		T396	2
values[22]	275	1			T502	1		T405	1		T396	2
values[23]	244	1			T502	1		T405	2		T396	2
values[24]	243	1			T502	1		T405	3		T396	2
values[25]	301	1			T502	1		T405	1		T396	2
values[26]	258	1			T502	1		T396	2		T432	6
values[27]	257	1			T502	1		T396	2		T432	6
values[28]	293	1			T502	1		T396	2		T432	6
values[29]	277	1			T502	1		T396	2		T432	13
values[30]	302	1			T502	1		T396	2		T432	18
values[31]	255	1			T502	1		T396	2		T432	4
values[32]	228	1			T502	1		T396	2		T432	7
values[33]	281	1			T502	1		T396	2		T432	9
values[34]	254	1			T502	1		T396	2		T432	9
values[35]	268	1			T502	1		T396	2		T432	19
values[36]	298	1			T502	1		T396	2		T432	3
values[37]	282	1			T502	1		T396	2		T432	5
values[38]	270	1			T502	1		T396	2		T432	10
values[39]	258	1			T502	1		T396	2		T432	9
values[40]	282	1			T502	1		T396	2		T432	3
values[41]	261	1			T502	1		T396	2		T432	5
values[42]	291	1			T502	1		T396	2		T432	14
values[43]	252	1			T502	1		T396	2		T432	4
values[44]	291	1			T502	1		T396	2		T432	10
values[45]	264	1			T502	1		T396	2		T432	6
values[46]	311	1			T502	1		T396	2		T432	1
values[47]	268	1			T502	1		T396	2		T808	1
values[48]	257	1			T502	1		T396	2		T808	1
values[49]	232	1			T502	1		T396	2		T808	1
values[50]	194	1			T502	1		T396	2		T808	1
values[51]	223	1			T502	1		T396	2		T808	1
values[52]	246	1			T502	1		T396	2		T808	1
values[53]	204	1			T502	1		T396	2		T808	1
values[54]	203	1			T502	1		T396	2		T808	1
values[55]	201	1			T502	1		T396	2		T808	1
values[56]	257	1			T502	1		T396	3		T808	1
values[57]	254	1			T502	1		T396	2		T808	1
values[58]	221	1			T502	1		T396	2		T808	1
values[59]	192	1			T502	1		T396	2		T808	1
values[60]	215	1			T502	1		T396	2		T808	1
values[61]	238	1			T502	1		T396	2		T808	1
values[62]	213	1			T502	1		T396	2		T808	1
values[63]	216	1			T502	1		T396	2		T808	1
values[64]	201	1			T502	1		T396	2		T808	1
values[65]	184	1			T502	1		T396	2		T808	1
values[66]	205	1			T502	1		T396	2		T808	1
values[67]	183	1			T502	1		T396	2		T808	1
values[68]	181	1			T502	1		T396	2		T808	1
values[69]	196	1			T502	1		T396	2		T808	1
values[70]	199	1			T502	1		T396	2		T808	1
values[71]	139	1			T502	1		T396	2		T808	1
values[72]	146	1			T502	1		T396	2		T808	1
values[73]	149	1			T502	1		T396	2		T808	1
values[74]	111	1			T502	1		T396	2		T808	1
values[75]	104	1			T502	1		T396	2		T808	1
values[76]	93	1			T502	1		T396	2		T808	1
values[77]	80	1			T502	1		T396	2		T808	1
values[78]	102	1			T502	1		T396	2		T808	1
values[79]	89	1			T502	1		T396	2		T808	1
values[80]	106	1			T502	6		T396	2		T808	1
values[81]	91	1			T502	3		T396	2		T808	1
values[82]	93	1			T502	4		T396	3		T808	1
values[83]	112	1			T502	13		T396	2		T808	1
values[84]	110	1			T502	2		T396	2		T808	1
values[85]	103	1			T502	1		T396	3		T808	1
values[86]	89	1			T502	1		T396	2		T808	1
values[87]	100	1			T502	2		T396	2		T808	1
values[88]	79	1			T502	2		T396	2		T808	1
values[89]	82	1			T502	3		T396	2		T808	1
values[90]	110	1			T502	8		T396	2		T808	3
values[91]	113	1			T502	5		T396	2		T808	2
values[92]	106	1			T502	4		T396	2		T808	1
values[93]	125	1			T502	5		T396	2		T808	4
values[94]	83	1			T502	1		T396	2		T808	2
values[95]	93	1			T502	2		T396	2		T808	10
values[96]	80	1			T502	1		T396	2		T808	1
values[97]	64	1			T502	2		T396	2		T808	3
values[98]	77	1			T502	3		T396	2		T808	1
values[99]	72	1			T502	2		T396	2		T808	7
values[100]	86	1			T502	9		T396	2		T808	1
values[101]	93	1			T502	1		T396	2		T808	1
values[102]	97	1			T502	3		T396	6		T808	1
values[103]	88	1			T502	1		T396	4		T808	1
values[104]	71	1			T502	1		T396	2		T808	1
values[105]	74	1			T502	1		T396	3		T808	3
values[106]	62	1			T502	1		T396	6		T808	1
values[107]	72	1			T502	4		T396	2		T808	2
values[108]	79	1			T502	2		T396	3		T808	2
values[109]	68	1			T502	1		T396	2		T808	1
values[110]	82	1			T502	3		T396	3		T808	2
values[111]	69	1			T502	2		T396	4		T808	1
values[112]	92	1			T502	1		T396	2		T808	1
values[113]	94	1			T502	1		T396	4		T808	6
values[114]	69	1			T502	1		T396	4		T808	3
values[115]	73	1			T502	2		T396	3		T808	3
values[116]	75	1			T502	4		T396	6		T808	5
values[117]	66	1			T502	1		T396	5		T808	2
values[118]	59	1			T502	3		T396	3		T808	2
values[119]	66	1			T502	7		T396	5		T808	2
values[120]	71	1			T502	1		T396	2		T808	2
values[121]	73	1			T502	3		T396	5		T808	1
values[122]	79	1			T502	2		T396	2		T808	1
values[123]	76	1			T502	2		T396	5		T808	1
values[124]	73	1			T502	2		T396	4		T808	8
values[125]	52	1			T502	2		T396	2		T808	1
values[126]	97	1			T502	3		T396	2		T808	2
values[127]	995	1			T502	39		T396	41		T808	31
values[128]	9112	1			T502	289		T396	515		T808	286