Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136276	1			T74	75		T76	11		T78	5
values[2]	8926	1			T74	4		T80	13		T508	3
values[3]	3615	1			T80	13		T416	1		T396	3
values[4]	2174	1			T80	8		T416	1		T396	3
values[5]	1373	1			T80	7		T416	1		T396	4
values[6]	1034	1			T80	6		T416	1		T396	3
values[7]	838	1			T80	5		T416	1		T396	3
values[8]	755	1			T80	11		T416	1		T396	3
values[9]	544	1			T80	12		T416	1		T396	3
values[10]	444	1			T80	11		T416	1		T396	3
values[11]	436	1			T80	4		T416	1		T396	3
values[12]	401	1			T80	6		T416	1		T396	3
values[13]	373	1			T80	10		T416	1		T396	3
values[14]	357	1			T80	14		T416	1		T396	4
values[15]	318	1			T80	3		T416	1		T396	3
values[16]	308	1			T80	4		T416	1		T396	3
values[17]	364	1			T80	9		T416	1		T396	3
values[18]	369	1			T80	12		T416	1		T396	3
values[19]	314	1			T80	5		T416	1		T396	3
values[20]	283	1			T80	10		T416	1		T396	3
values[21]	338	1			T80	13		T416	1		T396	3
values[22]	344	1			T80	15		T416	1		T396	3
values[23]	325	1			T80	9		T416	1		T396	3
values[24]	292	1			T80	5		T416	1		T396	3
values[25]	296	1			T80	5		T416	1		T396	3
values[26]	278	1			T80	10		T416	1		T396	3
values[27]	298	1			T80	7		T416	1		T396	3
values[28]	342	1			T80	7		T416	1		T396	3
values[29]	328	1			T80	5		T416	1		T396	3
values[30]	345	1			T80	13		T416	1		T396	4
values[31]	291	1			T80	17		T416	1		T396	3
values[32]	336	1			T80	18		T416	1		T396	3
values[33]	363	1			T80	2		T416	1		T396	3
values[34]	271	1			T80	5		T416	1		T396	3
values[35]	287	1			T80	3		T416	1		T396	3
values[36]	272	1			T80	4		T416	1		T396	3
values[37]	273	1			T80	8		T416	1		T396	3
values[38]	307	1			T80	4		T416	1		T396	3
values[39]	311	1			T80	7		T416	1		T396	3
values[40]	313	1			T80	5		T416	1		T396	3
values[41]	272	1			T80	21		T416	1		T396	3
values[42]	291	1			T80	22		T416	1		T396	4
values[43]	311	1			T80	9		T416	1		T396	3
values[44]	286	1			T80	4		T416	1		T396	3
values[45]	262	1			T80	4		T416	1		T396	3
values[46]	289	1			T80	10		T416	1		T396	3
values[47]	305	1			T80	7		T416	1		T396	3
values[48]	287	1			T80	20		T416	1		T396	3
values[49]	271	1			T80	5		T416	1		T396	3
values[50]	280	1			T80	13		T416	1		T396	3
values[51]	277	1			T80	5		T416	1		T396	3
values[52]	282	1			T80	12		T416	1		T396	3
values[53]	233	1			T80	4		T416	1		T396	3
values[54]	226	1			T80	4		T416	1		T396	3
values[55]	242	1			T80	3		T416	1		T396	3
values[56]	275	1			T80	5		T416	1		T396	3
values[57]	224	1			T80	3		T416	1		T396	3
values[58]	223	1			T80	8		T416	1		T396	3
values[59]	186	1			T80	10		T416	1		T396	3
values[60]	199	1			T80	3		T416	1		T396	3
values[61]	221	1			T80	3		T416	1		T396	3
values[62]	186	1			T80	12		T416	2		T396	3
values[63]	198	1			T80	1		T416	2		T396	3
values[64]	180	1			T416	1		T396	3		T432	4
values[65]	162	1			T416	1		T396	3		T432	3
values[66]	169	1			T416	1		T396	3		T432	8
values[67]	168	1			T416	1		T396	3		T432	9
values[68]	142	1			T416	1		T396	4		T432	3
values[69]	127	1			T416	1		T396	3		T432	3
values[70]	170	1			T416	1		T396	3		T432	5
values[71]	134	1			T416	1		T396	3		T432	6
values[72]	141	1			T416	1		T396	3		T447	2
values[73]	132	1			T416	1		T396	3		T447	4
values[74]	147	1			T416	1		T396	3		T447	6
values[75]	120	1			T416	1		T396	3		T447	1
values[76]	129	1			T416	1		T396	3		T447	2
values[77]	89	1			T416	1		T396	3		T447	2
values[78]	113	1			T416	1		T396	3		T447	1
values[79]	101	1			T416	1		T396	3		T447	3
values[80]	111	1			T416	1		T396	3		T447	3
values[81]	109	1			T416	1		T396	3		T447	1
values[82]	96	1			T416	1		T396	3		T447	1
values[83]	102	1			T416	1		T396	3		T447	5
values[84]	94	1			T416	1		T396	3		T447	1
values[85]	83	1			T416	1		T396	3		T447	2
values[86]	101	1			T416	1		T396	3		T447	9
values[87]	100	1			T416	1		T396	3		T447	5
values[88]	109	1			T416	1		T396	3		T447	3
values[89]	112	1			T416	1		T396	4		T447	1
values[90]	105	1			T416	1		T396	8		T447	7
values[91]	85	1			T416	1		T396	4		T447	1
values[92]	90	1			T416	1		T396	4		T447	2
values[93]	92	1			T416	1		T396	3		T447	4
values[94]	104	1			T416	1		T396	9		T447	4
values[95]	107	1			T416	1		T396	3		T447	4
values[96]	140	1			T416	1		T396	3		T447	4
values[97]	101	1			T416	1		T396	7		T447	6
values[98]	86	1			T416	1		T396	6		T447	3
values[99]	106	1			T416	1		T396	3		T447	1
values[100]	96	1			T416	1		T396	7		T447	2
values[101]	87	1			T416	1		T396	4		T447	1
values[102]	114	1			T416	1		T396	7		T447	1
values[103]	99	1			T416	1		T396	4		T447	1
values[104]	103	1			T416	1		T396	4		T447	2
values[105]	104	1			T416	1		T396	5		T447	1
values[106]	99	1			T416	1		T396	9		T447	2
values[107]	110	1			T416	1		T396	7		T447	3
values[108]	100	1			T416	1		T396	3		T447	2
values[109]	101	1			T416	1		T396	6		T447	2
values[110]	82	1			T416	1		T396	5		T447	2
values[111]	94	1			T416	1		T396	5		T447	4
values[112]	80	1			T416	1		T396	7		T447	1
values[113]	82	1			T416	1		T396	8		T447	2
values[114]	116	1			T416	1		T396	4		T447	1
values[115]	98	1			T416	1		T396	4		T447	1
values[116]	108	1			T416	1		T396	4		T447	6
values[117]	102	1			T416	1		T396	8		T447	11
values[118]	97	1			T416	1		T396	4		T447	5
values[119]	99	1			T416	1		T396	3		T447	2
values[120]	117	1			T416	1		T396	8		T447	13
values[121]	104	1			T416	1		T396	4		T447	9
values[122]	79	1			T416	1		T396	4		T447	2
values[123]	96	1			T416	1		T396	7		T447	1
values[124]	98	1			T416	1		T396	4		T447	4
values[125]	104	1			T416	1		T396	7		T466	4
values[126]	185	1			T416	3		T396	9		T466	4
values[127]	1180	1			T416	41		T396	81		T466	13
values[128]	10361	1			T416	396		T396	829		T466	244