Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134172	1			T74	91		T75	1		T76	12
values[2]	8738	1			T74	4		T75	1		T502	1
values[3]	3589	1			T75	1		T502	1		T80	10
values[4]	2019	1			T75	2		T502	1		T80	5
values[5]	1346	1			T75	1		T502	1		T80	6
values[6]	931	1			T75	1		T502	1		T80	8
values[7]	673	1			T75	1		T502	1		T80	4
values[8]	553	1			T75	1		T502	1		T80	7
values[9]	533	1			T75	1		T502	1		T80	7
values[10]	393	1			T75	1		T502	1		T80	8
values[11]	412	1			T75	1		T502	1		T80	12
values[12]	396	1			T75	1		T502	1		T80	16
values[13]	396	1			T75	1		T502	1		T80	5
values[14]	310	1			T75	1		T502	1		T80	3
values[15]	335	1			T75	1		T502	1		T80	6
values[16]	346	1			T75	1		T502	1		T80	14
values[17]	323	1			T75	1		T502	1		T80	13
values[18]	373	1			T75	1		T502	1		T80	4
values[19]	329	1			T75	1		T502	1		T80	3
values[20]	277	1			T75	1		T502	1		T80	6
values[21]	309	1			T75	1		T502	1		T80	7
values[22]	294	1			T75	1		T502	1		T80	7
values[23]	299	1			T75	1		T502	1		T80	7
values[24]	309	1			T75	1		T502	1		T80	4
values[25]	338	1			T75	1		T502	1		T80	10
values[26]	354	1			T75	1		T502	1		T80	24
values[27]	309	1			T75	1		T502	1		T80	6
values[28]	300	1			T75	1		T502	1		T80	3
values[29]	337	1			T75	1		T502	1		T80	12
values[30]	352	1			T75	1		T502	1		T80	4
values[31]	294	1			T75	1		T502	1		T80	9
values[32]	332	1			T75	1		T502	1		T80	13
values[33]	364	1			T75	1		T502	1		T80	9
values[34]	336	1			T75	1		T502	1		T80	5
values[35]	308	1			T75	1		T502	1		T80	7
values[36]	298	1			T75	1		T502	1		T80	8
values[37]	323	1			T75	1		T502	1		T80	8
values[38]	325	1			T75	1		T502	1		T80	6
values[39]	310	1			T75	1		T502	1		T80	4
values[40]	314	1			T75	1		T502	1		T80	13
values[41]	330	1			T75	1		T502	1		T80	2
values[42]	316	1			T75	1		T502	1		T80	15
values[43]	323	1			T75	1		T502	1		T80	21
values[44]	308	1			T75	1		T502	1		T80	12
values[45]	306	1			T75	1		T502	1		T80	4
values[46]	323	1			T75	1		T502	1		T80	7
values[47]	328	1			T75	1		T502	1		T80	4
values[48]	335	1			T75	1		T502	1		T80	4
values[49]	303	1			T75	1		T502	1		T80	20
values[50]	311	1			T75	1		T502	1		T80	15
values[51]	310	1			T75	1		T502	1		T80	7
values[52]	233	1			T75	1		T502	1		T80	6
values[53]	239	1			T75	1		T502	2		T805	19
values[54]	267	1			T75	1		T502	1		T805	15
values[55]	261	1			T75	1		T502	1		T805	15
values[56]	271	1			T75	1		T502	1		T805	13
values[57]	224	1			T75	1		T502	1		T805	7
values[58]	237	1			T75	1		T502	1		T805	7
values[59]	225	1			T75	1		T502	1		T805	11
values[60]	209	1			T75	1		T502	1		T805	16
values[61]	224	1			T75	1		T502	1		T805	23
values[62]	160	1			T75	1		T502	1		T805	10
values[63]	160	1			T75	1		T502	1		T805	7
values[64]	134	1			T75	1		T502	1		T805	7
values[65]	148	1			T75	1		T502	1		T805	13
values[66]	150	1			T75	1		T502	1		T805	12
values[67]	150	1			T75	1		T502	1		T805	9
values[68]	142	1			T75	1		T502	1		T805	5
values[69]	86	1			T75	1		T502	1		T805	4
values[70]	132	1			T75	1		T502	1		T805	10
values[71]	140	1			T75	1		T502	1		T805	23
values[72]	110	1			T75	1		T502	1		T805	8
values[73]	104	1			T75	1		T502	1		T805	17
values[74]	97	1			T75	1		T502	1		T805	4
values[75]	105	1			T75	1		T502	1		T396	1
values[76]	85	1			T75	1		T502	1		T396	1
values[77]	83	1			T75	1		T502	1		T396	1
values[78]	57	1			T75	1		T502	1		T396	1
values[79]	63	1			T75	1		T502	1		T396	1
values[80]	73	1			T75	1		T502	1		T396	1
values[81]	63	1			T75	1		T502	1		T396	1
values[82]	62	1			T75	1		T502	1		T396	1
values[83]	82	1			T75	1		T502	1		T396	1
values[84]	87	1			T75	1		T502	1		T396	1
values[85]	61	1			T75	1		T502	1		T396	1
values[86]	66	1			T75	1		T502	1		T396	1
values[87]	65	1			T75	2		T502	1		T396	1
values[88]	67	1			T75	1		T502	1		T396	1
values[89]	59	1			T75	1		T502	1		T396	1
values[90]	79	1			T75	1		T502	1		T396	1
values[91]	58	1			T75	1		T502	1		T396	2
values[92]	70	1			T75	1		T502	1		T396	5
values[93]	80	1			T75	1		T502	1		T396	1
values[94]	57	1			T75	1		T502	1		T396	2
values[95]	65	1			T75	1		T502	1		T396	10
values[96]	60	1			T75	1		T502	1		T396	4
values[97]	76	1			T75	1		T502	1		T396	3
values[98]	71	1			T75	1		T502	3		T396	3
values[99]	90	1			T75	1		T502	7		T396	8
values[100]	82	1			T75	1		T502	2		T396	1
values[101]	69	1			T75	1		T502	2		T396	2
values[102]	75	1			T75	1		T502	2		T396	1
values[103]	86	1			T75	1		T502	2		T396	1
values[104]	81	1			T75	1		T502	4		T396	2
values[105]	77	1			T75	1		T502	5		T396	2
values[106]	59	1			T75	1		T502	3		T396	1
values[107]	88	1			T75	1		T502	7		T396	2
values[108]	95	1			T75	1		T502	5		T396	3
values[109]	81	1			T75	1		T502	2		T396	1
values[110]	101	1			T75	1		T502	2		T396	3
values[111]	86	1			T75	1		T502	1		T396	3
values[112]	72	1			T75	1		T502	3		T396	1
values[113]	60	1			T75	1		T502	1		T396	2
values[114]	73	1			T75	1		T502	2		T396	3
values[115]	75	1			T75	1		T502	2		T396	2
values[116]	61	1			T75	1		T502	1		T396	2
values[117]	71	1			T75	1		T502	1		T396	4
values[118]	81	1			T75	1		T502	3		T396	2
values[119]	73	1			T75	1		T502	3		T396	1
values[120]	71	1			T75	1		T502	3		T396	2
values[121]	66	1			T75	1		T502	1		T396	5
values[122]	59	1			T75	3		T502	4		T396	1
values[123]	53	1			T75	1		T502	2		T396	2
values[124]	57	1			T75	1		T502	1		T396	4
values[125]	64	1			T75	1		T502	1		T396	1
values[126]	114	1			T75	2		T502	4		T396	1
values[127]	897	1			T75	23		T502	30		T396	26
values[128]	8972	1			T75	283		T502	271		T396	332