Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	154865	1			T74	83		T76	12		T79	14
values[2]	4235	1			T74	1		T502	1		T508	4
values[3]	2200	1			T502	1		T665	1		T525	31
values[4]	1579	1			T502	1		T665	1		T525	30
values[5]	1265	1			T502	1		T665	1		T525	32
values[6]	1126	1			T502	1		T665	1		T525	21
values[7]	952	1			T502	1		T665	1		T525	11
values[8]	873	1			T502	1		T665	1		T525	17
values[9]	704	1			T502	1		T665	1		T525	6
values[10]	653	1			T502	1		T665	1		T525	8
values[11]	491	1			T502	1		T665	1		T525	14
values[12]	389	1			T502	1		T665	1		T525	15
values[13]	458	1			T502	1		T665	1		T525	11
values[14]	380	1			T502	1		T665	1		T525	20
values[15]	382	1			T502	1		T665	1		T525	16
values[16]	347	1			T502	1		T665	1		T525	11
values[17]	296	1			T502	1		T665	1		T525	7
values[18]	258	1			T502	1		T665	1		T525	12
values[19]	223	1			T502	1		T665	1		T525	17
values[20]	224	1			T502	1		T665	1		T525	12
values[21]	272	1			T502	1		T665	1		T525	24
values[22]	243	1			T502	1		T665	1		T525	19
values[23]	234	1			T502	1		T665	1		T525	17
values[24]	208	1			T502	1		T665	1		T525	19
values[25]	219	1			T502	1		T665	1		T525	15
values[26]	187	1			T502	1		T665	1		T525	31
values[27]	159	1			T502	1		T665	1		T525	31
values[28]	148	1			T502	1		T665	1		T525	35
values[29]	131	1			T502	1		T665	1		T525	33
values[30]	127	1			T502	1		T665	1		T525	28
values[31]	129	1			T502	1		T665	1		T525	17
values[32]	178	1			T502	1		T665	1		T525	25
values[33]	188	1			T502	1		T665	1		T525	59
values[34]	180	1			T502	1		T665	1		T525	59
values[35]	130	1			T502	1		T665	1		T525	25
values[36]	121	1			T502	1		T665	1		T525	24
values[37]	109	1			T502	1		T665	1		T525	36
values[38]	97	1			T502	1		T665	1		T525	21
values[39]	100	1			T502	1		T665	1		T525	5
values[40]	83	1			T502	1		T665	1		T525	6
values[41]	67	1			T502	1		T665	1		T799	1
values[42]	95	1			T502	1		T665	1		T799	1
values[43]	86	1			T502	1		T665	1		T799	1
values[44]	61	1			T502	1		T665	1		T799	1
values[45]	50	1			T502	1		T665	1		T799	1
values[46]	45	1			T502	1		T665	1		T799	1
values[47]	50	1			T502	1		T665	1		T799	1
values[48]	46	1			T502	1		T665	1		T799	1
values[49]	55	1			T502	1		T665	1		T799	2
values[50]	52	1			T502	1		T665	1		T799	1
values[51]	52	1			T502	1		T665	1		T799	1
values[52]	47	1			T502	1		T665	1		T799	1
values[53]	40	1			T502	1		T665	1		T799	1
values[54]	46	1			T502	1		T665	1		T799	1
values[55]	51	1			T502	1		T665	1		T799	1
values[56]	47	1			T502	1		T665	1		T799	1
values[57]	40	1			T502	1		T665	1		T799	1
values[58]	49	1			T502	1		T665	1		T799	1
values[59]	46	1			T502	1		T665	1		T799	1
values[60]	46	1			T502	1		T665	1		T799	1
values[61]	37	1			T502	1		T665	1		T799	1
values[62]	43	1			T502	1		T665	2		T799	1
values[63]	45	1			T502	1		T665	1		T799	1
values[64]	56	1			T502	1		T665	1		T799	1
values[65]	57	1			T502	1		T665	1		T799	1
values[66]	51	1			T502	1		T665	1		T799	1
values[67]	48	1			T502	1		T665	1		T799	1
values[68]	42	1			T502	1		T665	1		T799	1
values[69]	42	1			T502	1		T665	1		T799	1
values[70]	52	1			T502	1		T665	1		T799	1
values[71]	58	1			T502	1		T665	1		T799	1
values[72]	61	1			T502	1		T665	1		T799	1
values[73]	59	1			T502	1		T665	1		T799	1
values[74]	41	1			T502	1		T665	1		T799	1
values[75]	44	1			T502	1		T665	1		T799	1
values[76]	48	1			T502	1		T665	1		T799	1
values[77]	46	1			T502	1		T665	1		T799	1
values[78]	48	1			T502	1		T665	1		T799	1
values[79]	64	1			T502	1		T665	1		T799	1
values[80]	64	1			T502	1		T665	1		T799	1
values[81]	62	1			T502	1		T665	1		T799	1
values[82]	72	1			T502	1		T665	1		T799	1
values[83]	68	1			T502	1		T665	1		T799	1
values[84]	66	1			T502	1		T665	1		T799	1
values[85]	72	1			T502	1		T665	1		T799	1
values[86]	59	1			T502	1		T665	1		T799	1
values[87]	64	1			T502	1		T665	1		T799	1
values[88]	74	1			T502	1		T665	1		T799	1
values[89]	56	1			T502	1		T665	1		T799	1
values[90]	61	1			T502	1		T665	1		T799	1
values[91]	77	1			T502	1		T665	1		T799	1
values[92]	66	1			T502	1		T665	1		T799	1
values[93]	73	1			T502	1		T665	1		T799	1
values[94]	71	1			T502	1		T665	1		T799	1
values[95]	72	1			T502	1		T665	1		T799	1
values[96]	80	1			T502	1		T665	1		T799	1
values[97]	71	1			T502	1		T665	1		T799	1
values[98]	77	1			T502	1		T665	1		T799	1
values[99]	54	1			T502	1		T665	1		T799	1
values[100]	61	1			T502	1		T665	1		T799	1
values[101]	70	1			T502	1		T665	1		T799	1
values[102]	60	1			T502	1		T665	1		T799	1
values[103]	74	1			T502	3		T665	1		T799	1
values[104]	70	1			T502	3		T665	1		T799	1
values[105]	71	1			T502	2		T665	1		T799	1
values[106]	81	1			T502	2		T665	1		T799	1
values[107]	84	1			T502	4		T665	1		T799	1
values[108]	94	1			T502	5		T665	1		T799	1
values[109]	95	1			T502	3		T665	1		T799	1
values[110]	100	1			T502	2		T665	1		T799	1
values[111]	88	1			T502	2		T665	1		T799	1
values[112]	84	1			T502	3		T665	1		T799	1
values[113]	82	1			T502	2		T665	2		T799	1
values[114]	81	1			T502	2		T665	1		T799	1
values[115]	91	1			T502	2		T665	3		T799	4
values[116]	79	1			T502	2		T665	1		T799	3
values[117]	74	1			T502	2		T665	4		T799	2
values[118]	77	1			T502	4		T665	1		T799	1
values[119]	106	1			T502	2		T665	2		T799	2
values[120]	87	1			T502	2		T665	1		T799	1
values[121]	94	1			T502	1		T665	6		T799	1
values[122]	107	1			T502	1		T665	3		T799	2
values[123]	110	1			T502	1		T665	3		T799	1
values[124]	199	1			T502	3		T665	1		T799	4
values[125]	314	1			T502	4		T665	3		T799	5
values[126]	725	1			T502	26		T665	15		T799	18
values[127]	2575	1			T502	135		T665	98		T799	143
values[128]	4335	1			T502	221		T665	192		T799	184