Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150274	1			T74	78		T75	1		T76	10
values[2]	3803	1			T74	3		T75	1		T78	1
values[3]	1728	1			T75	1		T416	1		T525	12
values[4]	1116	1			T75	1		T416	1		T525	10
values[5]	827	1			T75	1		T416	1		T525	6
values[6]	705	1			T75	1		T416	1		T525	21
values[7]	674	1			T75	1		T416	1		T525	44
values[8]	598	1			T75	1		T416	1		T525	22
values[9]	613	1			T75	1		T416	1		T525	12
values[10]	562	1			T75	1		T416	1		T525	1
values[11]	552	1			T75	1		T416	1		T396	1
values[12]	448	1			T75	1		T416	1		T396	1
values[13]	466	1			T75	1		T416	1		T396	1
values[14]	504	1			T75	1		T416	1		T396	1
values[15]	453	1			T75	1		T416	1		T396	1
values[16]	333	1			T75	1		T416	1		T396	1
values[17]	242	1			T75	1		T416	1		T396	1
values[18]	228	1			T75	1		T416	1		T396	1
values[19]	265	1			T75	1		T416	1		T396	1
values[20]	206	1			T75	1		T416	1		T396	1
values[21]	172	1			T75	1		T416	1		T396	1
values[22]	143	1			T75	1		T416	1		T396	1
values[23]	160	1			T75	1		T416	1		T396	1
values[24]	139	1			T75	1		T416	1		T396	1
values[25]	126	1			T75	1		T416	1		T396	1
values[26]	112	1			T75	1		T416	1		T396	1
values[27]	131	1			T75	1		T416	1		T396	1
values[28]	138	1			T75	1		T416	1		T396	1
values[29]	106	1			T75	1		T416	1		T396	1
values[30]	112	1			T75	1		T416	1		T396	1
values[31]	113	1			T75	1		T416	1		T396	1
values[32]	99	1			T75	1		T416	1		T396	1
values[33]	95	1			T75	1		T416	1		T396	1
values[34]	81	1			T75	1		T416	1		T396	1
values[35]	106	1			T75	2		T416	1		T396	1
values[36]	95	1			T75	1		T416	1		T396	1
values[37]	82	1			T75	1		T416	1		T396	1
values[38]	94	1			T75	1		T416	1		T396	1
values[39]	108	1			T75	2		T416	1		T396	1
values[40]	105	1			T75	1		T416	1		T396	1
values[41]	109	1			T75	1		T416	1		T396	1
values[42]	99	1			T75	1		T416	1		T396	1
values[43]	117	1			T75	1		T416	1		T396	1
values[44]	88	1			T75	1		T416	1		T396	1
values[45]	87	1			T75	1		T416	1		T396	1
values[46]	84	1			T75	1		T416	1		T396	1
values[47]	89	1			T75	1		T416	1		T396	1
values[48]	92	1			T75	1		T416	1		T396	1
values[49]	74	1			T75	1		T416	1		T396	1
values[50]	69	1			T75	1		T416	1		T396	1
values[51]	79	1			T75	1		T416	1		T396	1
values[52]	84	1			T75	1		T416	1		T396	1
values[53]	77	1			T75	1		T416	1		T396	1
values[54]	83	1			T75	1		T416	1		T396	1
values[55]	96	1			T75	1		T416	1		T396	1
values[56]	75	1			T75	1		T416	1		T396	1
values[57]	72	1			T75	1		T416	1		T396	1
values[58]	72	1			T75	1		T416	1		T396	1
values[59]	84	1			T75	1		T416	1		T396	1
values[60]	83	1			T75	1		T416	1		T396	1
values[61]	82	1			T75	1		T416	1		T396	1
values[62]	76	1			T75	1		T416	1		T396	1
values[63]	86	1			T75	1		T416	1		T396	1
values[64]	83	1			T75	1		T416	1		T396	1
values[65]	83	1			T75	1		T416	1		T396	2
values[66]	72	1			T75	1		T416	1		T396	1
values[67]	75	1			T75	1		T416	1		T396	1
values[68]	76	1			T75	1		T416	1		T396	1
values[69]	68	1			T75	1		T416	1		T396	1
values[70]	76	1			T75	1		T416	1		T396	1
values[71]	69	1			T75	1		T416	1		T396	1
values[72]	75	1			T75	1		T416	1		T396	1
values[73]	78	1			T75	1		T416	1		T396	1
values[74]	98	1			T75	1		T416	1		T396	1
values[75]	100	1			T75	1		T416	1		T396	1
values[76]	108	1			T75	1		T416	1		T396	1
values[77]	118	1			T75	1		T416	1		T396	1
values[78]	94	1			T75	1		T416	1		T396	1
values[79]	96	1			T75	1		T416	1		T396	1
values[80]	99	1			T75	1		T416	1		T396	1
values[81]	107	1			T75	1		T416	1		T396	1
values[82]	111	1			T75	1		T416	1		T396	1
values[83]	117	1			T75	1		T416	1		T396	1
values[84]	116	1			T75	1		T416	1		T396	1
values[85]	116	1			T75	1		T416	2		T396	1
values[86]	121	1			T75	1		T416	1		T396	1
values[87]	101	1			T75	1		T416	3		T396	1
values[88]	114	1			T75	1		T416	5		T396	1
values[89]	127	1			T75	1		T416	9		T396	1
values[90]	119	1			T75	1		T416	2		T396	1
values[91]	102	1			T75	1		T416	3		T396	1
values[92]	108	1			T75	1		T416	1		T396	1
values[93]	112	1			T75	1		T416	1		T396	1
values[94]	109	1			T75	1		T416	1		T396	1
values[95]	101	1			T75	1		T416	1		T396	1
values[96]	112	1			T75	1		T416	1		T396	1
values[97]	114	1			T75	2		T416	2		T396	1
values[98]	94	1			T75	1		T416	2		T396	1
values[99]	110	1			T75	1		T416	1		T396	1
values[100]	124	1			T75	1		T416	2		T396	1
values[101]	120	1			T75	1		T416	1		T396	1
values[102]	131	1			T75	1		T416	4		T396	1
values[103]	110	1			T75	4		T416	3		T396	1
values[104]	131	1			T75	10		T416	2		T396	1
values[105]	136	1			T75	3		T416	1		T396	1
values[106]	134	1			T75	1		T416	1		T396	1
values[107]	113	1			T75	3		T416	4		T396	1
values[108]	123	1			T75	4		T416	3		T396	1
values[109]	113	1			T75	2		T416	2		T396	1
values[110]	125	1			T75	3		T416	6		T396	1
values[111]	130	1			T75	2		T416	5		T396	1
values[112]	142	1			T75	1		T416	3		T396	1
values[113]	152	1			T75	5		T416	1		T396	1
values[114]	154	1			T75	2		T416	2		T396	1
values[115]	128	1			T75	2		T416	1		T396	1
values[116]	141	1			T75	6		T416	2		T396	1
values[117]	137	1			T75	1		T416	2		T396	1
values[118]	159	1			T75	1		T416	7		T396	1
values[119]	164	1			T75	3		T416	2		T396	1
values[120]	152	1			T75	4		T416	2		T396	1
values[121]	147	1			T75	1		T416	1		T396	1
values[122]	127	1			T75	1		T416	1		T396	1
values[123]	169	1			T75	1		T416	2		T396	1
values[124]	266	1			T75	2		T416	1		T396	2
values[125]	508	1			T75	1		T416	3		T396	6
values[126]	1130	1			T75	22		T416	11		T396	23
values[127]	4094	1			T75	136		T416	93		T396	119
values[128]	7612	1			T75	230		T416	226		T396	267