Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136607	1			T74	54		T76	8		T78	4
values[2]	8814	1			T502	2		T80	104		T508	3
values[3]	3200	1			T502	2		T80	26		T405	47
values[4]	1858	1			T502	2		T80	8		T405	30
values[5]	1199	1			T502	2		T80	12		T405	17
values[6]	817	1			T502	2		T80	7		T405	18
values[7]	580	1			T502	2		T80	5		T405	11
values[8]	516	1			T502	2		T80	11		T405	15
values[9]	451	1			T502	2		T80	8		T405	8
values[10]	456	1			T502	2		T80	10		T405	16
values[11]	421	1			T502	2		T80	13		T405	9
values[12]	406	1			T502	2		T80	8		T405	8
values[13]	387	1			T502	2		T80	15		T405	5
values[14]	397	1			T502	2		T80	6		T405	3
values[15]	377	1			T502	3		T80	4		T416	1
values[16]	321	1			T502	2		T80	6		T416	1
values[17]	308	1			T502	2		T80	5		T416	1
values[18]	362	1			T502	2		T80	9		T416	1
values[19]	364	1			T502	2		T80	11		T416	1
values[20]	350	1			T502	2		T80	8		T416	1
values[21]	332	1			T502	2		T80	7		T416	1
values[22]	292	1			T502	2		T80	5		T416	1
values[23]	366	1			T502	2		T80	4		T416	1
values[24]	333	1			T502	2		T80	4		T416	1
values[25]	337	1			T502	2		T80	9		T416	1
values[26]	350	1			T502	2		T80	6		T416	1
values[27]	319	1			T502	2		T80	5		T416	1
values[28]	304	1			T502	2		T80	6		T416	1
values[29]	263	1			T502	2		T416	1		T396	1
values[30]	323	1			T502	2		T416	1		T396	1
values[31]	282	1			T502	2		T416	1		T396	1
values[32]	329	1			T502	2		T416	1		T396	1
values[33]	357	1			T502	2		T416	1		T396	1
values[34]	274	1			T502	2		T416	1		T396	1
values[35]	287	1			T502	2		T416	1		T396	1
values[36]	288	1			T502	2		T416	1		T396	1
values[37]	284	1			T502	2		T416	1		T396	1
values[38]	264	1			T502	2		T416	1		T396	1
values[39]	274	1			T502	2		T416	1		T396	1
values[40]	325	1			T502	2		T416	1		T396	1
values[41]	322	1			T502	2		T416	1		T396	1
values[42]	267	1			T502	2		T416	1		T396	1
values[43]	303	1			T502	2		T416	1		T396	1
values[44]	281	1			T502	2		T416	2		T396	1
values[45]	256	1			T502	2		T416	1		T396	1
values[46]	278	1			T502	2		T416	1		T396	1
values[47]	256	1			T502	2		T416	1		T396	1
values[48]	207	1			T502	2		T416	1		T396	1
values[49]	238	1			T502	2		T416	1		T396	1
values[50]	216	1			T502	2		T416	1		T396	1
values[51]	247	1			T502	2		T416	1		T396	1
values[52]	283	1			T502	2		T416	1		T396	1
values[53]	274	1			T502	2		T416	1		T396	1
values[54]	271	1			T502	2		T416	1		T396	1
values[55]	253	1			T502	2		T416	1		T396	1
values[56]	226	1			T502	2		T416	1		T396	1
values[57]	265	1			T502	2		T416	1		T396	1
values[58]	207	1			T502	2		T416	1		T396	1
values[59]	203	1			T502	2		T416	1		T396	1
values[60]	179	1			T502	2		T416	1		T396	1
values[61]	190	1			T502	2		T416	1		T396	1
values[62]	202	1			T502	2		T416	1		T396	1
values[63]	140	1			T502	2		T416	1		T396	1
values[64]	133	1			T502	2		T416	1		T396	1
values[65]	122	1			T502	2		T416	1		T396	1
values[66]	104	1			T502	2		T416	1		T396	1
values[67]	132	1			T502	2		T416	1		T396	1
values[68]	103	1			T502	2		T416	1		T396	1
values[69]	105	1			T502	2		T416	1		T396	1
values[70]	77	1			T502	2		T416	1		T396	1
values[71]	80	1			T502	2		T416	1		T396	1
values[72]	60	1			T502	2		T416	1		T396	1
values[73]	65	1			T502	2		T416	1		T396	1
values[74]	71	1			T502	2		T416	1		T396	1
values[75]	60	1			T502	2		T416	1		T396	1
values[76]	62	1			T502	2		T416	1		T396	1
values[77]	76	1			T502	2		T416	1		T396	1
values[78]	74	1			T502	2		T416	1		T396	1
values[79]	57	1			T502	2		T416	1		T396	1
values[80]	57	1			T502	2		T416	1		T396	1
values[81]	53	1			T502	2		T416	1		T396	1
values[82]	48	1			T502	2		T416	1		T396	1
values[83]	56	1			T502	2		T416	1		T396	1
values[84]	60	1			T502	3		T416	1		T396	1
values[85]	54	1			T502	2		T416	1		T396	1
values[86]	59	1			T502	2		T416	1		T396	1
values[87]	64	1			T502	2		T416	1		T396	1
values[88]	63	1			T502	2		T416	1		T396	1
values[89]	84	1			T502	2		T416	1		T396	1
values[90]	68	1			T502	2		T416	1		T396	1
values[91]	66	1			T502	2		T416	1		T396	1
values[92]	66	1			T502	2		T416	1		T396	1
values[93]	66	1			T502	2		T416	1		T396	1
values[94]	68	1			T502	3		T416	1		T396	1
values[95]	45	1			T502	4		T416	1		T396	1
values[96]	46	1			T502	3		T416	1		T396	1
values[97]	41	1			T502	3		T416	1		T396	1
values[98]	55	1			T502	2		T416	1		T396	1
values[99]	71	1			T502	3		T416	1		T396	1
values[100]	52	1			T502	2		T416	1		T396	1
values[101]	74	1			T502	2		T416	1		T396	1
values[102]	73	1			T502	3		T416	1		T396	1
values[103]	74	1			T502	4		T416	2		T396	1
values[104]	56	1			T502	3		T416	1		T396	1
values[105]	60	1			T502	3		T416	1		T396	1
values[106]	56	1			T502	2		T416	2		T396	1
values[107]	75	1			T502	3		T416	2		T396	3
values[108]	68	1			T502	4		T416	1		T396	3
values[109]	76	1			T502	5		T416	2		T396	3
values[110]	53	1			T502	5		T416	3		T396	2
values[111]	57	1			T502	4		T416	1		T396	3
values[112]	60	1			T502	4		T416	2		T396	5
values[113]	63	1			T502	4		T416	1		T396	3
values[114]	42	1			T502	3		T416	1		T396	1
values[115]	77	1			T502	4		T416	8		T396	5
values[116]	63	1			T502	3		T416	1		T396	1
values[117]	64	1			T502	4		T416	1		T396	1
values[118]	49	1			T502	3		T416	1		T396	2
values[119]	53	1			T502	5		T416	5		T396	1
values[120]	62	1			T502	5		T416	1		T396	4
values[121]	69	1			T502	2		T416	5		T396	3
values[122]	60	1			T502	2		T416	2		T396	3
values[123]	62	1			T502	7		T416	1		T396	2
values[124]	74	1			T502	3		T416	1		T396	5
values[125]	61	1			T502	4		T416	1		T396	1
values[126]	85	1			T502	5		T416	1		T396	2
values[127]	772	1			T502	68		T416	34		T396	33
values[128]	6615	1			T502	565		T416	337		T396	328