Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134394	1			T74	86		T76	15		T78	1
values[2]	9014	1			T74	1		T502	1		T80	113
values[3]	3564	1			T502	1		T80	18		T805	5
values[4]	2103	1			T502	1		T805	7		T829	12
values[5]	1430	1			T502	1		T805	12		T829	6
values[6]	932	1			T502	1		T805	4		T432	3
values[7]	718	1			T502	1		T805	6		T432	2
values[8]	488	1			T502	1		T805	6		T432	3
values[9]	525	1			T502	1		T805	5		T432	12
values[10]	390	1			T502	1		T805	10		T432	7
values[11]	400	1			T502	1		T805	8		T432	11
values[12]	333	1			T502	1		T805	6		T432	5
values[13]	375	1			T502	1		T805	21		T432	3
values[14]	386	1			T502	1		T805	5		T432	9
values[15]	389	1			T502	1		T805	8		T432	10
values[16]	339	1			T502	1		T805	5		T432	8
values[17]	327	1			T502	1		T805	6		T432	8
values[18]	347	1			T502	1		T805	11		T432	5
values[19]	320	1			T502	1		T805	7		T432	19
values[20]	336	1			T502	1		T805	4		T432	6
values[21]	327	1			T502	1		T805	4		T432	4
values[22]	313	1			T502	1		T805	5		T432	5
values[23]	386	1			T502	1		T805	28		T432	4
values[24]	329	1			T502	1		T805	6		T432	3
values[25]	307	1			T502	1		T805	5		T432	3
values[26]	310	1			T502	1		T805	5		T432	5
values[27]	305	1			T502	1		T805	11		T432	5
values[28]	316	1			T502	1		T805	5		T432	18
values[29]	331	1			T502	1		T805	9		T432	19
values[30]	335	1			T502	1		T805	9		T432	4
values[31]	322	1			T502	1		T805	5		T432	2
values[32]	295	1			T502	1		T805	14		T432	12
values[33]	309	1			T502	1		T805	6		T432	4
values[34]	293	1			T502	1		T805	4		T432	4
values[35]	327	1			T502	1		T805	9		T432	2
values[36]	328	1			T502	1		T805	3		T432	14
values[37]	278	1			T502	1		T805	3		T432	5
values[38]	336	1			T502	1		T805	2		T432	5
values[39]	367	1			T502	1		T805	13		T432	19
values[40]	295	1			T502	1		T805	10		T432	7
values[41]	380	1			T502	1		T805	39		T432	4
values[42]	369	1			T502	1		T805	8		T432	12
values[43]	327	1			T502	1		T805	2		T432	3
values[44]	356	1			T502	1		T805	5		T432	5
values[45]	372	1			T502	1		T805	5		T432	3
values[46]	335	1			T502	1		T805	5		T432	3
values[47]	289	1			T502	1		T805	3		T432	10
values[48]	326	1			T502	1		T805	8		T432	13
values[49]	255	1			T502	1		T805	5		T432	15
values[50]	271	1			T502	1		T805	2		T432	16
values[51]	250	1			T502	1		T805	15		T432	6
values[52]	294	1			T502	1		T805	7		T432	4
values[53]	282	1			T502	1		T805	10		T432	5
values[54]	292	1			T502	1		T805	13		T432	1
values[55]	256	1			T502	1		T805	7		T664	3
values[56]	258	1			T502	1		T805	7		T664	3
values[57]	231	1			T502	1		T805	5		T664	2
values[58]	233	1			T502	1		T805	10		T664	1
values[59]	228	1			T502	1		T805	11		T664	3
values[60]	216	1			T502	1		T805	10		T664	1
values[61]	207	1			T502	1		T805	6		T664	3
values[62]	224	1			T502	1		T805	4		T664	1
values[63]	190	1			T502	1		T805	6		T664	7
values[64]	184	1			T502	1		T805	20		T664	4
values[65]	174	1			T502	1		T664	6		T481	5
values[66]	166	1			T502	1		T664	2		T481	8
values[67]	157	1			T502	1		T664	7		T481	14
values[68]	131	1			T502	1		T664	3		T481	17
values[69]	136	1			T502	1		T664	1		T481	25
values[70]	135	1			T502	1		T664	2		T481	8
values[71]	114	1			T502	1		T664	1		T481	6
values[72]	101	1			T502	1		T664	3		T481	2
values[73]	92	1			T502	1		T664	2		T812	1
values[74]	92	1			T502	1		T664	3		T812	1
values[75]	72	1			T502	1		T664	3		T812	1
values[76]	96	1			T502	1		T664	1		T812	1
values[77]	83	1			T502	1		T664	1		T812	1
values[78]	94	1			T502	1		T664	2		T812	1
values[79]	74	1			T502	1		T664	5		T812	1
values[80]	75	1			T502	1		T664	1		T812	1
values[81]	90	1			T502	1		T664	3		T812	1
values[82]	82	1			T502	1		T664	4		T812	1
values[83]	66	1			T502	1		T664	1		T812	1
values[84]	59	1			T502	1		T664	1		T812	1
values[85]	73	1			T502	1		T664	2		T812	1
values[86]	64	1			T502	1		T664	1		T812	1
values[87]	85	1			T502	1		T664	4		T812	1
values[88]	77	1			T502	1		T664	4		T812	1
values[89]	68	1			T502	1		T664	4		T812	1
values[90]	66	1			T502	1		T664	2		T812	1
values[91]	69	1			T502	1		T664	1		T812	1
values[92]	70	1			T502	1		T664	2		T812	1
values[93]	54	1			T502	1		T664	4		T812	1
values[94]	64	1			T502	1		T664	1		T812	1
values[95]	51	1			T502	1		T664	3		T812	1
values[96]	69	1			T502	1		T664	7		T812	1
values[97]	74	1			T502	1		T664	3		T812	1
values[98]	90	1			T502	1		T664	3		T812	1
values[99]	78	1			T502	2		T664	1		T812	1
values[100]	78	1			T502	2		T664	3		T812	1
values[101]	93	1			T502	7		T664	3		T812	1
values[102]	60	1			T502	2		T664	3		T812	1
values[103]	63	1			T502	2		T664	2		T812	1
values[104]	72	1			T502	2		T664	4		T812	1
values[105]	62	1			T502	1		T664	5		T812	2
values[106]	54	1			T502	3		T664	2		T812	2
values[107]	61	1			T502	4		T664	4		T812	1
values[108]	77	1			T502	4		T664	7		T812	1
values[109]	57	1			T502	4		T664	2		T812	2
values[110]	67	1			T502	2		T664	6		T812	1
values[111]	78	1			T502	3		T664	9		T812	1
values[112]	67	1			T502	2		T664	1		T812	5
values[113]	82	1			T502	3		T664	3		T812	9
values[114]	59	1			T502	3		T664	2		T812	1
values[115]	61	1			T502	2		T664	1		T812	5
values[116]	78	1			T502	1		T664	4		T812	1
values[117]	56	1			T502	1		T664	5		T812	3
values[118]	77	1			T502	2		T664	4		T812	1
values[119]	79	1			T502	2		T664	3		T812	5
values[120]	67	1			T502	1		T664	4		T812	1
values[121]	68	1			T502	3		T664	3		T812	1
values[122]	59	1			T502	1		T664	4		T812	2
values[123]	67	1			T502	6		T812	1		T831	1
values[124]	66	1			T502	4		T812	2		T831	1
values[125]	81	1			T502	1		T812	1		T831	1
values[126]	146	1			T502	1		T812	1		T831	2
values[127]	854	1			T502	31		T812	38		T831	37
values[128]	6764	1			T502	276		T812	365		T831	356